Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

Abstract: This application provides a live streaming processing method performed by an electronic device. The method includes: displaying a live streaming room, the live stream room having a host account, a host sub-account and multiple viewer accounts, the host sub-account being used for assisting the host account of the live streaming room in operation; receiving real-time live streaming data of the live streaming room, and displaying a live streaming content on a live streaming room page according to the real-time live streaming data, the real-time live streaming data collected from the host account and the viewer accounts; and displaying, in response to a live streaming room operation of the host sub-account, an operation result of the live streaming room operation of the host sub-account in the live streaming room, wherein the operation result of the live streaming room operation updates the live streaming content on the live streaming room page.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

Abstract: This application provides a power supply circuit and a control method for a control circuit, where the power supply circuit includes a voltage buck-boost adjustment circuit and a control circuit, and the control circuit is coupled to the voltage buck-boost adjustment circuit. The control circuit is configured to: when a voltage value of a first enable signal of the voltage buck-boost adjustment circuit is greater than or equal to a first predetermined value, control the output voltage of the voltage buck-boost adjustment circuit to be a first output voltage, and is further configured to: when the voltage value of the first enable signal of the voltage buck-boost adjustment circuit is less than or equal to a second predetermined value, control the output voltage of the voltage buck-boost adjustment circuit to be a second output voltage or a zero voltage, where the first predetermined value is greater than the second predetermined value, and the first output voltage is higher than the second output voltage.

Abstract: A flush toilet, comprising a washing water supply portion which has a water outlet and a water inlet configured to connect to an external water supply pipe, is disclosed. Water flowing in from the water inlet flows from a first water inlet pipe to a second water inlet pipe, and then flows from the second water inlet pipe to the water outlet, a flow sectional area of the first water inlet pipe is smaller than a flow sectional area of the water inlet, and a flow sectional area of the second water inlet pipe is larger than the flow sectional area of the first water inlet pipe.

Abstract: Embodiments of the present application provide a stator, comprising a coil group is provided with a first end part, a second end part, multiple coils respectively wound on a multiple teeth, and a transition line part configured to connect multiple coils, the first end part is provided with a first overlapping part having the same position as at least a part of the second end part in the circumferential direction, the second end part is provided with a second overlapping part having the same position as the first overlapping part in the circumferential direction, and a coil connecting part is connected with the first overlapping part and the second overlapping part.

Abstract: A processor chip includes a logic circuit. The logic circuit is configured to be coupled to an electronic device. A configuration of the logic circuit corresponds to a plurality of candidate configurations. The configuration of the logic circuit is switched among the candidate configurations, and the electronic device associates with the processor chip to implement a function corresponding to the configuration of the logic circuit. When the configuration of the logic circuit is a first configuration and the electronic device executes a first driver program, the function is a first network-connection function. When the configuration of the logic circuit is a second configuration and the electronic device executes a second driver program, the function is a second network-connection function different from the first network-connection function.

Abstract: An augmented reality display device including a virtual image display and a controller is provided. The virtual image display is configured to provide a left eye virtual image and a right eye virtual image to a left eye and a right eye of a user, respectively. The controller is electrically connected to the virtual image display, and is configured to command the virtual image display to display a left eye virtual mark and a right eye virtual mark, corresponding to a real mark in space, in the left eye virtual image and the right eye virtual image, respectively, and calculate an interpupillary distance between the left eye and the right eye according to a deviation of the left eye virtual mark with respect to the real mark and a deviation of the right eye virtual mark with respect to the real mark.

Abstract: A cell purification module, configured to purify multiple cells from a fluid sample is provided. The cell purification module includes a hollow column, multiple hollow fiber membranes, at least one first magnetic component, a fluid sample inlet end, and a fluid sample outlet end. The hollow column has a first opening, a second opening, and an accommodating space connecting the first opening and the second opening. The hollow fiber membranes are disposed in the accommodating space and each hollow fiber membrane has multiple pores. The first magnetic component is disposed at a periphery of the hollow column. The fluid sample inlet end and the fluid sample outlet end are respectively disposed at two ends of the hollow column. The hollow fiber membranes extend in an axial direction of the hollow column, and are arranged in a radial direction of the hollow column. A cell purification system is also provided.

Abstract: The present invention relates to a control system for a network device. The control system comprises a network device for connecting to a network and transmitting status information of the network device; a host server for receiving the status information via the network and transmitting action information related to the network device, wherein the action information includes at least an action command; and a Message Queuing Telemetry Transport (MQTT) server for receiving the action information from the host server, and transmitting the action information to the network device, wherein the network device executes the action command according to the received action information.

Abstract: A multiplexing circuit, an interface circuit system, and a mobile terminal, to resolve a problem that a charging current significantly decreases when a headset is used during charging of the mobile terminal. In a multiplexing circuit, a first switch circuit transmits a right-channel audio signal on a right-channel transmission end to a first external transmission end; a second switch circuit transmits a left-channel audio signal on a left-channel transmission end to a second external transmission end; when a second on voltage is received, but a first on voltage is not received, an isolation circuit transmits the second on voltage to a third switch circuit; and when the first on voltage and the second on voltage are received, the isolation circuit pulls down the third switch circuit, and isolates a ground end from a second on voltage end.

Abstract: A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.

Abstract: An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A low-cost and low-voltage anti-fuse array includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistor of all anti-fuse memory cells includes an anti-fuse gate commonly used by other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit-lines, wherein the anti-fuse memory cells in the same row are connected to different bit-lines, and all anti-fuse memory cells are connected to the same selection-line and different word-lines. The present invention utilizes the configuration of common source contacts to achieve a stable source structure and reduce the overall layout area, and meanwhile minimizes the types of control voltage to reduce leakage current.

Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.

Abstract: A color compensation method includes obtaining a target brightness, a target frame rate and a target pulse number; selecting a plurality of second gamma groups from a plurality of first gamma groups according to the target brightness and the target pulse number, wherein the plurality of first gamma groups respectively correspond to a plurality of frame rates; and calculating the compensation value to compensate the display brightness and color according to the target brightness, the target frame rate, the plurality of second gamma groups and a calculation method.

Abstract: A head mounted display including two display units is provided. An included angle between the two display units is greater than 0 degrees and less than 180 degrees. Each of the two display units includes a display device, a condenser lens and a prism. The condenser lens overlaps the display device. The prism overlaps the condenser lens and the display device. A material of one of the condenser lens and the prism includes flint glass, and a material of the other of the condenser lens and the prism includes crown glass.

Abstract: Augmented reality glasses including a first image source, a second image source and a lens set are provided. The first image source emits a first image beam. The second image source emits a second image beam. The lens set includes a first lens and a second lens and disposed on the path of the image beams. A gap is disposed between the first lens and the second lens. The refractive index of the gap is lower than that of the first lens. The image beams enter the lens set at an incident surface of the lens set, are reflected at a first surface of the first lens, and exit the lens set at an exit surface. The optical path length of the first image beam from the first image source to the eyes is different from that of the second image beam from the second image source to the eyes.