Patents by Inventor Ting Lin

Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250062083
    Abstract: A key structure includes a base, an elastic member disposed on the base, a scissors structure movably disposed on the base, and a keycap module having a carrier and a light source. The carrier is detachably assembled to the scissors structure and abuts the elastic member. The light source is disposed in the carrier. The light source is electrically connected to a bottom portion of the base through a flexible circuit member penetrating the carrier, passing the scissors structure, and penetrating the base. A top portion of the carrier has light transmittance, so that light of the light source can pass through the top portion to be projected from the key structure.
    Type: Application
    Filed: January 22, 2024
    Publication date: February 20, 2025
    Applicant: Acer Incorporated
    Inventors: Hung-Chi Chen, Cheng-Han Lin, Huei-Ting Chuang, Shun-Bin Chen
  • Patent number: 12228765
    Abstract: A curved optical plate includes a curved light exit surface including at least one curved edge and at least one uncurved edge, and at least one first side surface connected to the at least one uncurved edge of the light exit surface; a first side surface includes a first surface, and the first surface extends toward an interior of the curved optical plate.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: February 18, 2025
    Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuhang Lin, Zhiying Chen, Chengkun Liu, Han Zhang, Hongyu Zhao, Ming Chen, Zhijie Guo, Lian Fang, Long Hu, Ting Cui, Liangliang Ren, Kai Diao
  • Patent number: 12228809
    Abstract: A display module includes a back plate, a light guide plate, a rubber frame and a display panel, the light guide plate is fixed on a bearing surface, a connecting line between two end portions of the bearing surface forms a first curve. The first curve includes a circular arc segment and a transition curve segment, and bends in a direction away from the display panel; the circular arc segment is located at the middle, at least one end of the circular arc segment is provided with the transition curve segment; the transition curve segment is located at a first position, the first position being a position of the bearing surface opposite to a second position, the second position being a position where light leaks from the display panel, the radius of curvature of the transition curve increases along a direction close to an end portion of the first curve.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: February 18, 2025
    Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Han Zhang, Shuwen Lai, Kai Diao, Long Hu, Liangliang Ren, Yuhang Lin, Lian Fang, Chengkun Liu, Dingjie Zheng, Zhijie Guo, Zhiying Chen, Ting Cui
  • Patent number: 12230450
    Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.
    Type: Grant
    Filed: February 18, 2024
    Date of Patent: February 18, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Mao-Ying Wang, Yu-Ting Lin
  • Patent number: 12230537
    Abstract: A method for forming an interconnect structure includes forming a first conductive layer over a dielectric layer, forming one or more openings in the first conductive layer to expose portions of dielectric surface of the dielectric layer and conductive surfaces of the first conductive layer, wherein the one or more openings separates the first conductive layer into one or more portions.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Ya Lo, Cheng-Chin Lee, Shao-Kuan Lee, Chi-Lin Teng, Hsin-Yen Huang, Hsiaokang Chang, Shau-Lin Shue
  • Publication number: 20250056851
    Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Jen-Hong Chang, Yi-Hsiu Liu, You-Ting Lin, Chih-Chung Chang, Kuo-Yi Chao, Jiun-Ming Kuo, Yuan-Ching Peng, Sung-En Lin, Chia-Cheng Chao, Chung-Ting Ko
  • Publication number: 20250054786
    Abstract: A die bonding tool includes a bond head having a moveable component. The moveable component may be moveable between an extended position in which a lower surface of the moveable component protrudes below a lower surface of the bond head and a retracted position in which the lower surface of the moveable component does not protrude below the lower surface of the bond head. The moveable component may be used to control a shape of a semiconductor die secured to the lower surface of the bond head during a process of bonding the semiconductor die to a substrate. Accordingly, void areas and other bonding defects may be avoided and the bond formed between the semiconductor die and the target substrate may be improved.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Inventors: Chih-Yuan Chiu, Chi-Chun Peng, Yu-Hong Du, Hui-Ting Lin, Jen-Hao Liu, Amram Eitan
  • Publication number: 20250052511
    Abstract: A vapor chamber heatsink assembly, under vacuum, having a working fluid therein, comprising a plurality of heatsink fins and a vapor chamber is provided. The vapor chamber comprises an upper and lower casing having an upper and lower chamber surface, respectively. The upper and lower chamber surfaces define a plurality of obstructers forming a plurality of braided channels therearound. When heat from a greater temperature heat source and a lower temperature heat source is applied to respective contact surfaces of the lower casing, via the plurality of obstructers and braided channels, respectively, the working fluid and liquid vapor slugs/bubbles travel therethrough, providing an effective phase change mechanism to the greater temperature heat source, while concurrently, hindering agglomeration of working fluid thereto. An effective phase change mechanism is also concurrently provided to the lower temperature heat source due to the non-agglomeration of working fluid to the greater temperature heat source.
    Type: Application
    Filed: October 24, 2024
    Publication date: February 13, 2025
    Inventors: Chia yu Lin, Shan yin Cheng, Chien ting Liu
  • Publication number: 20250054894
    Abstract: A device includes a first die, an interconnect structure, a RDL layer, a guard structure and an underfill layer. The interconnect structure is electrically connected to the first die. The RDL layer is disposed in a dielectric layer. The guard structure is disposed in the dielectric layer to define a connector region, wherein the guard structure and the interconnect structure are disposed on opposite sides of the die. The underfill layer surrounds the interconnect structure, the first die and the guard structure, wherein the underfill layer is kept outside of the connector region by the guard structure.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua-Wei Tseng, Yueh-Ting Lin, Shao-Yun Chen, Li-Hsien Huang, An-Jhih Su, Ming-Shih Yeh, Der-Chyang Yeh
  • Patent number: 12221516
    Abstract: A method for degrading polyethylene terephthalate is provided. The method includes: providing polyethylene terephthalate material, providing a catalyst composite including a porous carrier having a pore size of 45 ? to 250 ? and a metal compound including at least one selected from a group consisting of zinc oxide, zinc hydroxide, zinc carbonate, magnesium oxide, calcium oxide, zirconium oxide, and titanium dioxide, in which the metal oxide is loaded on the porous carrier; and performing a degradation reaction, in which the polyethylene terephthalate material is reacted with the catalyst composite in the presence of an alcohol solvent.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: February 11, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Wei Hsu, Ssu-Ting Lin, Ying-Chieh Lee
  • Patent number: 12224352
    Abstract: A thin film transistor includes a stack of an active layer, a gate dielectric, and a gate electrode in a forward or in a reverse order. The active layer includes a compound semiconductor material containing oxygen, at least one acceptor-type element selected from Ga and W, and at least one heavy post-transition metal element selected from In and Sn. An atomic percentage of the at least one heavy post-transition metal element at a first surface portion of the active layer that contacts the gate dielectric is higher than an atomic percentage of the at least one heavy post-transition metal element at a second surface portion of the active layer located on an opposite side of the gate dielectric. The front channel current may be increased, and the back channel leakage current may be decreased.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wu-Wei Tsai, Hai-Ching Chen, Po-Ting Lin
  • Publication number: 20250044547
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a fixed portion, a movable portion and a driving assembly. The fixed portion has a main axis and includes a case and a bottom. The case is made of a non-metal material. The bottom is connected to the case. The case and the bottom are arranged along the main axis. The movable portion moves relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: Yen-Cheng CHEN, Meng-Ting LIN, Guan-Bo WANG, Sheng-Chang LIN, Sin-Jhong SONG
  • Publication number: 20250046673
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: Shao-Kuan Lee, Cherng-Shiaw Tsai, Ting-Ya Lo, Cheng-Chin Lee, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
  • Publication number: 20250048711
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed in a recess between two adjacent channel regions, wherein the S/D feature comprises an epitaxial layer conformally deposited on an exposed surface of the recess. The structure also includes a silicide layer conformally disposed on the S/D feature, and a S/D contact disposed on the silicide layer, wherein the S/D contact has a first portion extending into the recess, and the first portion has at least three surfaces being surrounded by the silicide layer and the S/D feature.
    Type: Application
    Filed: December 4, 2023
    Publication date: February 6, 2025
    Inventors: Chung-Ting KO, Shu Ling LIAO, Sung-En LIN
  • Publication number: 20250044668
    Abstract: A tripod-head structure includes a first clamping plate, a second clamping plate, a rotating base, a tightening element, and an adjustment component. The first clamping plate includes a first arc-shaped groove, and the second clamping plate includes a second arc-shaped groove. A portion of a slide rail of the rotating base is placed between the first arc-shaped groove and the second arc-shaped groove. The tightening element passes through the first clamping plate and the second clamping plate. The adjustment component is connected to the tightening element and switchable between an unlocked position and a locked position. In the unlocked position, the slide rail is slidable to adjust an angle of the rotating base. In the locked position, the tightening element presses the first clamping plate and the second clamping plate to tightly secure the slide rail for rapid adjustment of the angle of the rotating base.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Tzu-Yu LIN, Ching-Jung LAI, Yen-Ting LAI
  • Publication number: 20250047311
    Abstract: In some examples, the disclosure describes an electronic device with a processing resource and a memory resource storing computer-readable instructions executable by the processing resource to determine a wireless metric associated with a first wireless signal path utilizing concurrent dual wireless bands between an access point and the electronic device and alter the first wireless signal path to a second wireless signal path that utilizes a single band between the access point and the electronic device.
    Type: Application
    Filed: December 17, 2021
    Publication date: February 6, 2025
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Cheng-Fang Lin, Huai-Yung Yen, Ruei-Ting Lin, Ren-Hao Chen, Lo-Chun Tung, Yao-Cheng Yang
  • Patent number: 12219731
    Abstract: A centrifugal heat dissipation fan of a portable electronic device. The centrifugal heat dissipation fan includes a hub, multiple metal blades, and at least one ring. The metal blades are disposed surrounding the hub. The metal blades include multiple radial dimensions, and the structure of the metal blade with a shorter radial dimension is a part of the structure of the metal blade with a longer radial dimension. The metal blades having different radial dimensions form at least two ring areas, and the distribution numbers of the metal blades in the at least two ring areas are different from each other. The ring surrounds the hub and connects the metal blades.
    Type: Grant
    Filed: October 13, 2023
    Date of Patent: February 4, 2025
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen, Yu-Ming Lin
  • Patent number: 12215520
    Abstract: A lock device includes a latch and inner and outer operating devices disposed on two sides of the latch device. The inner operating device includes a main board configured to control the outer operating device to or not to move a latch between the latching position and the unlatching position. The outer operating device includes a removable input interface module electrically connectable with the main board. The input interface module is configured to permit input of an unlocking identification information or an unlocking command by a physical or wireless measure.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 4, 2025
    Assignee: I-TEK METAL MFG. CO., LTD.
    Inventor: Hsi-Ting Lin
  • Patent number: 12219880
    Abstract: A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.
    Type: Grant
    Filed: March 4, 2024
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Han-Ting Tsai, Chung-Te Lin
  • Patent number: 12219709
    Abstract: An integrated circuit (IC) chip assembly includes an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. The first structure is disposed over a first side of the first substrate. The second structure is disposed over a second side of the first substrate opposite the first side. The chip assembly includes a second substrate bonded to the IC die through the second side. The chip assembly includes a trench that extends through the second substrate and through the second structure of the IC die. Sidewalls of the trench are defined at least in part by one or more protective layers.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kao-Chih Liu, Wenmin Hsu, Yu-Ting Lin, Chia Hong Lin, ChienYi Chen