Abstract: Various embodiments include protection layers for a transistor and methods of forming the same. In an embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing a deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative a selective deposition process; depositing a protection layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protection material of the protection layer; and forming a gate structure around the semiconductor nanostructure.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: Provided is an isolated nucleic acid molecule comprising a NKp30 transmembrane domain, and a chimeric antigen receptor comprising the same. The isolated nucleic acid molecule comprising a NKp30 transmembrane domain comprises nucleic acid sequences encoding (a) an extracellular antigen binding domain, comprising a heavy chain variable region; (b) a hinge domain; (c) a NKp30 transmembrane domain; and (d) a NKp30 cytoplasmic domain. By introducing nucleic acid sequences of the NKp30 transmembrane domain and the NKp30 cytoplasmic domain in combination with the extracellular antigen binding domain into a T cell, the resulting CAR-T cell is a multi-chain CAR-T cell with a NKp30 receptor complex. Consequently, the resulting CAR-T cell forms stable immune synapses with cancer cells and exhibits excellent cytotoxicity against cancer cells.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Abstract: A manufacturing method of a transformer includes: winding a first winding wire around a bobbin, wherein two ends of the first winding wire are connected to a first and a second pin of the bobbin respectively; winding a second winding wire around the bobbin, wherein two ends of the second winding wire are connected to a third and a fourth pin of the bobbin respectively; and winding a third and a fourth winding wire in parallel around the bobbin, wherein two ends of the third winding wire are connected to the second and a fifth pin of the bobbin respectively, and two ends of the fourth winding wire are connected to the fifth and a sixth pin respectively. The first, the third and the fourth winding wires form a primary coil, and the second winding wire is a secondary coil.

Abstract: An asymmetric fused aromatic ring derivative containing sulfonyl group, which includes a structure represented by formula (I). Formula (I) is defined as in the specification. A use of the asymmetric fused aromatic ring derivative containing sulfonyl group, which is used as a photocatalyst. A hydrogen production device, which includes the asymmetric fused aromatic ring derivative containing sulfonyl group. An optoelectronic component, which includes the asymmetric fused aromatic ring derivative containing sulfonyl group.

Abstract: A fastener structure and an assembly method thereof are introduced. The fastener structure includes a body and a fastener. The body has a limiting structure and is for assembling at a first object. The fastener and the body are movably assembled. The fastener has a limiting portion, which coordinates with the limiting structure to limit a movement stroke of the fastener, so as to engage or disengage the fastener with or from a second object. Thus, the body can be assembled with the first object and the fastener can be engaged with or disengaged from the second object so as to complete quick coupling and separation of two objects, further achieving effects of repeated quick coupling and separation.

Abstract: A memory array device includes an array of memory cells located over a substrate, a memory-level dielectric layer laterally surrounding the array of memory cells, and top-interconnection metal lines laterally extending along a horizontal direction and contacting a respective row of top electrodes within the memory cells. Top electrodes of the memory cells are planarized to provide top surfaces that are coplanar with the top surface of the memory-level dielectric layer. The top-interconnection metal lines do not extend below the horizontal plane including the top surface of the memory-level dielectric layer, and prevent electrical shorts between the top-interconnection metal lines and components of memory cells.

Abstract: The present invention relates to an LC medium comprising two or more polymerizable compounds, at least one of which contains a substituent comprising a tertiary OH group, to its use for optical, electro-optical and electronic purposes, in particular in LC displays, especially in LC displays of the PSA (polymer sustained alignment) or SA (self-aligning) mode, to an LC display of the PSA or SA mode comprising the LC medium, and to a process of manufacturing the LC display using the LC medium, especially an energy-saving LC display and energy-saving LC display production process.

Abstract: A computing circuit with a de-identified architecture, a data computing method, a data processing system, and a data de-identification method are provided. The computing circuit includes an arithmetic array and a de-identification circuit. The computing circuit may perform an accumulation operation on input data to generate accumulated data by the arithmetic array. The de-identification circuit has an analog offset error determined based on an analog physical unclonable function. The computing circuit may operate the accumulated data according to the analog offset error to generate de-identification data by the de-identification circuit. It can not only provide the analog offset error through the transistors in the de-identification circuit, but also be combined with obfuscated code settings to dynamically adjusting the degree of de-identification of data.

Abstract: The present invention relates to an ultrasound image enhancement processing system and method thereof. The ultrasound image enhancement processing system includes at least one first ultrasound device and at least one server apparatus. The server apparatus receives a first ultrasound original image file, processes the first ultrasound original image file through a speckle reduction algorithm to generate a first processed image file, and performs a deep learning training on the first ultrasound original image file and the first processed image file to generate a first neural network model. The first neural network learning module is used to output a first speckle reduction enhancement image file. The image content of the first speckle reduction enhancement image file is approximating to the image content of the first processed image file.

Abstract: A package-on-package (PoP) structure includes a first package structure and a second package structure stacked on the first package structure. The first package structure includes a die, conductive structures, an encapsulant, and a conductive pattern layer. The conductive structures surround the die. The encapsulant laterally encapsulates the die and the conductive structures. The conductive pattern layer is disposed over and in physical contact with a top surface of the encapsulant and top surfaces of the conductive structures. An entire bottom surface of the conductive pattern layer is located at a same level height, and an entirety of the top surface of the encapsulant and an entirety of the top surfaces of the conductive structures are located at the same level height.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A semiconductor structure includes a semiconductor-on-insulator (SOI) substrate including a handle substrate, a buried insulating layer, and a top semiconductor layer; a first deep trench isolation structure that vertically extends through the top semiconductor layer and the buried insulating layer, and includes a first inner insulating liner laterally surrounding a first portion of the top semiconductor layer that is located in a first device region in a plan view, a first non-insulating moat structure laterally surrounding the first inner insulating liner, and a first outer insulating liner that laterally surrounds the first non-insulating moat structure; and a resistive memory array located on the first portion of the top semiconductor layer, and located entirely within the first device region in the plan view.

Abstract: A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

Abstract: A system for faster object attribute and/or intent classification may include an machine-learned (ML) architecture that processes temporal sensor data (e.g., multiple instances of sensor data received at different times) and includes a cache in an intermediate layer of the ML architecture. The ML architecture may be capable of classifying an object's intent to enter a roadway, idling near a roadway, or active crossing of a roadway. The ML architecture may additionally or alternatively classify indicator states, such as indications to turn, stop, or the like. Other attributes and/or intentions are discussed herein.