Patents by Inventor Ting Liu

Ting Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250022156
    Abstract: A pose calculating apparatus and method are provided. The pose calculating apparatus receives a plurality of real-time images and a plurality of inertial measurement parameters corresponding to at least one inertial sensor worn by a user. The pose calculating apparatus determines a pose calculating mode corresponding to each of a plurality of body regions of the user based on the real-time images and the inertial measurement parameters, wherein the pose calculating mode corresponds to a static mode or a motion mode. The pose calculating apparatus calculates a pose corresponding to each of the body regions based on the pose calculating mode corresponding to each of the body regions.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 16, 2025
    Inventors: Yen-Ting LIU, Yu-Heng HONG, Jia-Yau SHIAU
  • Publication number: 20250017282
    Abstract: An appliance heating control method and apparatus for user customizable vaping. The method comprises: acquiring appliance environment information and cigarette parameter information, and selecting, from a cigarette heating temperature curve library corresponding to the cigarette parameter information, an initial heating temperature curve that matches the appliance environment information; generating parameter adjustment guidance information on the basis of the initial heating temperature curve, and displaying the initial heating temperature curve and the parameter adjustment guidance information; and receiving a parameter adjustment instruction, adjusting the initial heating temperature curve on the basis of the parameter adjustment instruction, so as to obtain an adjusted heating temperature curve, and controlling, according to the adjusted heating temperature curve, an appliance to perform heating.
    Type: Application
    Filed: November 17, 2022
    Publication date: January 16, 2025
    Applicant: CHINA TOBACCO HUBEI INDUSTRIAL CORPORATION LIMITED
    Inventors: Ting HUANG, Huachen LIU, Jian TAN, Liangying TANG, Cong WU
  • Publication number: 20250024632
    Abstract: An airflow guiding mechanism includes a casing and an airflow guiding member. The airflow guiding member is rotatably disposed in the casing. The airflow guiding member is able to rotate between a first position and a second position. When the airflow guiding member is located at the first position, the airflow guiding member separates two airflow passages at opposite sides of the airflow guiding member from each other. When the airflow guiding member is located at the second position, the two airflow passages communicate with each other.
    Type: Application
    Filed: September 27, 2024
    Publication date: January 16, 2025
    Applicant: Wiwynn Corporation
    Inventors: Yuan-Shiang Ding, Geng-Ting Liu
  • Patent number: 12194054
    Abstract: The present application provides an application of Chidamide in combination with R-CHOP in preparing a drug used for treating B-cell lymphoma, and also provides a drug comprising Chidamide and R-CHOP. Chidamide in combination with R-CHOP has a synergistic therapeutic effect on B-cell lymphoma.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: January 14, 2025
    Assignees: SHENZHEN CHIPSCREEN BIOSCIENCES CO., LTD., RUI JIN HOSPITAL AFFILIATED TO SHANGHAI JIAO TONG UNIVERSITY SCHOOL OF MEDICINE
    Inventors: Xianping Lu, Weili Zhao, Xin Fu, Pengpeng Xu, Ting Liu
  • Patent number: 12200857
    Abstract: The present disclosure provides a package device including a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer, wherein the redistribution layer has a test mark, the test mark includes a conductive pattern formed of the conductive layer, the conductive pattern includes a center portion and a plurality of extension portions, and the plurality of extension portions are respectively connected to the center portion.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: January 14, 2025
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Publication number: 20250015007
    Abstract: One aspect of the present disclosure pertains to an integrated (IC) structure. The IC structure includes a semiconductor substrate; an interconnect structure formed over the substrate; and a redistribution layer (RDL) structure formed over the interconnect structure. The RDL structure includes: a RDL pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure; a RDL signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure; and a RDL top portion over the RDL pad portion and the RDL signal routing portion. The multiple vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width, the sacrificial via having a sacrificial via width, and the block via width is greater than the sacrificial via width.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Inventors: Yu-Chung Lai, Ying-Yao Lai, Chen-Chiu Huang, Hsiang-Ku Shen, Dian-Hau Chen, Kuo-An Liu, Tzu-Ting Liu
  • Patent number: 12193188
    Abstract: An immersion cooling system includes a tank, a first condenser, an enclosure, a second condenser and a connecting pipe. The tank has a first space. The first space is configured to accommodate a cooling liquid for at least one electronic equipment to immerse therein. The first condenser is disposed inside the tank. The enclosure is disposed outside the tank. The enclosure forms a second space together with the tank. The second condenser is disposed in the second space. The connecting pipe includes a first end and a second end opposite to the first end. The first end is connected with the second condenser. The second end is communicated with the first space.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: January 7, 2025
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chia-Yi Lin, Wei-Chih Lin, Ren-Chun Chang, Yan-Hui Jian, Hsuan-Ting Liu, Li-Hsiu Chen, Wen-Yin Tsai
  • Patent number: 12188883
    Abstract: This disclosure relates to an X-ray reflectometry apparatus and a method for measuring a three-dimensional nanostructure on a flat substrate. The X-ray reflectometry apparatus comprises an X-ray source, an X-ray reflector, a 2-dimensional X-ray detector, and a two-axis moving device. The X-ray source is for emitting X-ray. The X-ray reflector is configured for reflecting the X-ray onto a sample surface. The 2-dimensional X-ray detector is configured to collect a reflecting X-ray signal from the sample surface. The two-axis moving device is configured to control two-axis directions of the 2-dimensional X-ray detector to move on at least one of x-axis and z-axis with a formula concerning an incident angle of the X-ray with respect to the sample surface for collecting the reflecting X-ray signal.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: January 7, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Bo-Ching He, Chun-Ting Liu, Wei-En Fu, Wen-Li Wu
  • Patent number: 12190768
    Abstract: The present invention provides a method for ambient light detection, proximity sensing, and ambient light charging applied to a panel. The method includes: providing a display panel, wherein the display panel comprises a plurality of pixels with PN junctions units in a display area; and providing a driving circuit, wherein the driving circuit drives each display pixel or each PN junction unit through a display mode, a standby mode, and a blanking time, so that part of each display pixel or each PN junction unit is used to perform a display function and part of each display pixel or each PN junction unit is used to carry out the ambient light detection, proximity sensing, or ambient light charging.
    Type: Grant
    Filed: August 27, 2023
    Date of Patent: January 7, 2025
    Inventors: Yi-Jang Hsu, Yu-Ting Liu, Sheng-De Liu
  • Patent number: 12183712
    Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: December 31, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Che-Ting Liu, Jheng-Yu Hong, Yu-Ting Lu, Po-Chun Lee, Chih-Hsiang Hsu
  • Patent number: 12176251
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
  • Publication number: 20240420948
    Abstract: Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.
    Type: Application
    Filed: August 27, 2024
    Publication date: December 19, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Abhijeet S. Bagal, Qian Fu, Kuan-Ting Liu, Chung Liu
  • Publication number: 20240422942
    Abstract: An immersion cooling system is provided. The immersion cooling system includes a box, an upper cover, plural fixing components, plural latches and a link module. The box has an opening upwardly. The upper cover covers the opening. The fixing components are disposed on the box and arranged adjacent to the outer perimeter of the opening. The latches corresponding to the fixing components are disposed on the upper cover. The link module includes plural crossbars corresponding to the latches. The link module moves downwardly close to the upper cover, scroll-wheels of the latches roll along limiting surfaces of corresponding fixing components and press against the upper cover, the upper cover closes the opening to form an airtight space. The link module moves upwardly away from the upper cover, the scroll-wheels are separated away from the limiting surfaces of corresponding fixing components, allows the upper cover to separate from the opening.
    Type: Application
    Filed: July 27, 2023
    Publication date: December 19, 2024
    Inventors: Chia-Hsing Chen, Chen-Hsiu Lee, Hsuan-Ting Liu, Chiu-Chin Chang, Kuan-Lung Wu
  • Publication number: 20240418566
    Abstract: The present invention provides an ambient light sensor with ultraviolet light detection function, which is adopted to receive external light for sensing. The ambient light sensor comprises a visible light sensing chip and a wavelength conversion layer. The visible light sensing chip is used for sensing light corresponding to the response band of visible light, and the visible light sensing chip includes a light receiving surface. The wavelength conversion layer is used to convert light corresponding to a specific ultraviolet light band of the external light into light corresponding to a response band of visible light, and the wavelength conversion layer covers at least a part of the light receiving surface.
    Type: Application
    Filed: August 14, 2023
    Publication date: December 19, 2024
    Inventors: You-Hsien CHANG, Yan-Ting LIU
  • Patent number: 12170280
    Abstract: A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: December 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu
  • Publication number: 20240413059
    Abstract: A package structure and a method are provided. The package structure includes: a die pad; a plurality of discrete leads disposed on either side of or around the die pad, wherein each of the leads includes an upper surface and a lower surface, a trench extending through a portion of the lower surface and a portion of an outer sidewall surface of a lead being formed in a region, away from the die pad, of the lead, a lateral hole being formed in the lead on a side surface of the trench, the lateral hole communicating with the trench to form a step; a first molding layer filling the gaps between the leads and the die pad; a semiconductor chip disposed on an upper surface of the die pad; and a second molding layer disposed on an upper surface of the first molding layer, the lead, and the die pad.
    Type: Application
    Filed: June 6, 2024
    Publication date: December 12, 2024
    Applicant: JCET Group Co., Ltd.
    Inventors: Lei ZHENG, Ting LIU, Yuesheng ZHANG, Hu PU
  • Publication number: 20240389229
    Abstract: An electronic device includes a substrate, a first conductive structure, a second conductive structure, a first wire, and a second wire. The substrate includes a peripheral region. The first conductive structure is in the peripheral region and includes a first conductive layer and a second conductive layer. The first and the second conductive layer are arranged along a first direction. The second conductive structure is in the peripheral region and includes a third conductive layer. The first and the second conductive structure are arranged along a second direction, which is perpendicular to the first direction. The first wire is in the peripheral region and is electrically connected between the first and the third conductive layer. The second wire is in the peripheral region and is electrically connected to the second conductive layer. The first wire is adjacent to the second wire along the first direction.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Ting LIU, Yeong-E CHEN, Chean KEE
  • Patent number: 12148810
    Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
  • Patent number: 12148630
    Abstract: The application relates to a method for manufacturing an electronic device, and in particular, to a method for manufacturing an electronic device with a carrier substrate. The method includes: providing a carrier, forming a first base layer on the carrier; and forming working units on the first base layer. The working units are spaced apart from one another.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: November 19, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu, Cheng-Chi Wang
  • Patent number: 12148686
    Abstract: The present disclosure provides a package device and a manufacturing method thereof. The package device includes a redistribution layer which includes a first dielectric layer, a conductive layer and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test pattern that includes a first conductive pattern, and the first conductive pattern is formed of the conductive layer.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: November 19, 2024
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu