Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

Abstract: A preparation method of a flame-retardant ultrathin PEO-based solid electrolyte is disclosed. The method includes the following steps: preparing a CN support layer; synthesizing a flame retardant-loaded multifunctional filler: HNT@TMP; mixing and stirring PEO, LiTFSI, and HNT@TMP in a certain ratio in acetonitrile to obtain PEO-based solid electrolyte slurry; coating both sides of the CN support layer obtained in step S1 with the PEO-based solid electrolyte slurry obtained in step S3, and performing drying; and performing hot pressing to obtain a PEO-based solid electrolyte.

Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

Abstract: A flash memory controller includes a specific buffer and a processor. The specific buffer allocates a cache space. The processor receives a specific host address sent from the host device, reads and loads a corresponding address pointer mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer linker, determines a specific address pointer corresponding to the specific host address from the corresponding address pointer mapping table according to the specific host address, reads and loads a corresponding address mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer corresponding to the specific host address, and finds a specific flash memory address from the corresponding address mapping table according to the specific host address to perform an access operation in response to the found specific flash memory address.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

Abstract: Provided are a method and device for determining a reference timing, a storage medium and an electronic device. The method comprises: a second node determining a reference timing of the second node by using at least one of the following modes: an open-loop mode, a closed-loop mode and an external synchronization source mode. By means of the present disclosure, the problem in the related art that there is no technical solution for setting a reference timing between each-hop links yet exists is solved.

Abstract: A method for a three-dimensional temperature and salinity field, including: based on multi-source marine environmental data, analyzing the spatiotemporal distribution characteristics of marine dynamic environmental elements, and studying the characteristics of the temperature-salinity relation; on the basis of analysis of the spatiotemporal characteristics and study of the characteristics of the temperature-salinity relation, establishing a statistical prediction model of marine environmental dynamic elements by a spatiotemporal empirical orthogonal function method; based on the observation data of temperature and salinity obtained by the marine transportation platform, correcting a marine environment forecast field around the marine transportation platform by using a realtime analysis technology of a marine environment field; and adjusting the salinity using a temperature-salinity relation curve after the temperature and salinity are forecasted.

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Abstract: An error detection and correction device includes a decision-feedback equalizer (DFE), a decision circuit, an error detection circuit, and an error correction circuit. The DFE equalizes a data signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a symbol decision signal. The error detection circuit performs forward error detection at symbol positions of consecutive symbols included in the symbol decision signal to detect a head position of suspicious error that affects at least one symbol in the symbol decision signal. The error correction circuit performs error correction upon the symbol decision signal in response to the head position of the suspicious error that is detected by the error detection circuit.

Abstract: A method includes: receiving the semiconductor device, wherein the semiconductor device includes: a well region; a doped region; a plurality of gate electrodes; a plurality of source regions; and a plurality of drain regions, wherein the plurality of gate electrodes, the plurality of source region and the plurality of drain regions form a plurality of transistors; and a bulk region disposed in the doped region. A first distance measured between a first transistor of the plurality of transistors and the bulk region is greater than a second distance measured between a second transistor of the plurality of transistors and the bulk region. The method further includes: applying a first voltage to the plurality of drain regions, wherein a first avalanche current generated around the first transistor and shunted through the bulk region is greater than a second avalanche current generated around the second transistor and shunted through the bulk region.

Abstract: A method of the present disclosure includes forming a fin-shaped structure including a plurality of semiconductor layers, a first hard mask layer, a second hard mask layer, and a third hard mask layer, forming a patterned masking layer having a mask portion and a window portion, wherein the third hard mask layer is exposed through the window portion, performing a first etch process to expose the second hard mask layer through the window portion, performing a second etch process to etch the exposed second hard mask layer and to leave behind second hard mask layer residues, performing a third etch process to remove the second hard mask layer residues, etching the plurality of semiconductor layers in the fin-shaped structure through the window portion to divide the fin-shaped structure into a first segment and a second segment, and forming an isolation feature around the first segment and the second segment.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: A self-calibrating current measuring apparatus comprising a low-range current sensor configured to generate first voltage signals, a high-range current sensor configured to generate second voltage signals, and a self-calibration current measuring circuit configured to: receive the first voltage signals and the second voltage signals, convert the first voltage signals and the second voltage signals into respective first digital signals and second digital signals, compare the first digital signals with the second digital signals, determine a difference between the first digital signals and the second digital signals exceed a recalibration threshold based on the comparison, generate calibration data based on the determination, and generate a digital output signal representative of a current reading based on an application of the calibration data to the second digital signals.

Abstract: A method includes forming a first fin structure and a second fin structure protruding from a substrate, forming a dielectric fin between the first fin structure and the second fin structure, recessing the dielectric fin to form a trench between the first fin structure and the second fin structure, and depositing a first dielectric layer on sidewall surfaces of the trench and on a top surface of the recessed dielectric fin. After the depositing the first dielectric layer, a second dielectric layer is deposited in the trench. The method further includes depositing a third dielectric layer to cap the second dielectric layer in the trench, and forming a gate structure on the first fin structure, the second fin structure, and the third dielectric layer.

Abstract: The present disclosure discloses a pre-driver circuit and a driving device. The pre-driver circuit includes a first transistor, a second transistor, and a resistive component. The first transistor has a first terminal coupled to a first voltage, a second terminal for outputting a pre-driving signal, and a control terminal for receiving a first control signal. The second transistor has a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to a second voltage, and a control terminal for receiving the first control signal. The resistive component has a first terminal coupled to the first terminal of the second transistor, and a second terminal coupled to the second terminal of the second transistor. One of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor.

Abstract: The present application introduces a membrane fouling warning methodology grounded in machine learning. It utilizes a machine learning-based membrane fouling prediction model to automatically forecast and generate electrochemical information values, which characterize the extent of membrane fouling at various time points, based on influent water quality parameters. It then acquires the electrochemical information values Zt at a moment t and Zt+?t at a moment t+?t. Subsequently, it computes and assesses the respective fouling levels using the electrochemical information values derived from the membrane fouling prediction model. Finally, it issues an early warning signal contingent upon the determined warning level. This methodology facilitates proactive understanding and management of membrane fouling, thereby sustaining the normal operation of the membrane fouling treatment system, mitigating the propensity for membrane assembly fouling, and prolonging the operational lifespan of the membrane assembly.

Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.

Abstract: The present invention provides a control method of a display device, wherein the control method includes the steps of: connecting to an electronic device by using a first communication module, and receiving video signals from the electronic device to display on a display panel; and connecting to the electronic device by using a wireless communication module; and receiving a first control signal from an input device through a second communication module, generating a second control signal according to the first control signal, and transmitting the second control signal to the electronic device through the wireless communication module to control an operation of the electronic device.

Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.