Abstract: Snapshots for object storage buckets, including: receiving a command to generate a snapshot of a bucket of object storage of a storage system, wherein the snapshot records a state of the bucket at a particular point in time; and generating, in response to the command, the snapshot.

Abstract: A package structure and a method are provided. The package structure includes: a die pad; a plurality of discrete leads disposed on either side of or around the die pad, wherein each of the leads includes an upper surface and a lower surface, a trench extending through a portion of the lower surface and a portion of an outer sidewall surface of a lead being formed in a region, away from the die pad, of the lead, a lateral hole being formed in the lead on a side surface of the trench, the lateral hole communicating with the trench to form a step; a first molding layer filling the gaps between the leads and the die pad; a semiconductor chip disposed on an upper surface of the die pad; and a second molding layer disposed on an upper surface of the first molding layer, the lead, and the die pad.

Abstract: A method for manufacturing one or more optical sensor packages includes forming a bonded wafer by bonding (i) a device wafer comprising a plurality of optical sensing pixels and (ii) a circuit wafer comprising application-specific-integrated-circuit configured to operate the optical sensing pixels, where the bonded wafer includes a device-wafer surface and a circuit-wafer surface. The method also includes forming a plurality of microlens arrays over the device-wafer surface, where each microlens of the microlens arrays corresponds to a particular optical sensing pixel. The method also includes forming a plurality of module-lens structures over the plurality of microlens arrays, where each module-lens structure corresponds to a particular microlens array of the plurality of microlens arrays. The method also includes forming electrical contacts over the circuit-wafer surface to establish electrical connections to the plurality of optical sensing pixels and the application-specific-integrated-circuit.

Abstract: A wiring substrate, a manufacturing method thereof, a light-emitting panel, and a display device are disclosed. The wiring substrate includes: a base substrate (11); and a plurality of metal traces (50) and an organic insulating layer (13), which are located at one side of the base substrate. The metal traces (50) each comprise a first metal layer (141) and a second metal layer (151), which are stacked; the first metal layer (141) is located between the second metal layer (151) and the base substrate (11); an angle between a side wall of the second metal layer (151) and the base substrate (11) is greater than or equal to 90°; the area of a contact face between each of the metal traces (50) and the base substrate (11) is greater than or equal to the area of the surface of the second metal layer (151) opposite the first metal layer (141).

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.

Abstract: Provided are a data transmission method and apparatus, an information determination method and apparatus, and a storage medium. The data transmission method includes sending a paging message carrying first indication information to a second communication node, where the first indication information is used for indicating whether the second communication node is triggered to perform a mobile terminal-early data transmission (MT-EDT) procedure, and receiving a radio resource control (RRC) message carrying second indication information and sent by the second communication node.

Abstract: A display panel includes a substrate, first bonding electrodes, connecting leads, an electrode carrier plate and second bonding electrodes. The substrate includes a display surface, a non-display surface, and a selected side face. The display surface includes a first bonding area, and the non-display surface includes a second bonding area. The first bonding electrodes are arranged side by side at the intervals in the first bonding area. The connecting leads are arranged side by side at intervals, each connecting lead includes a first portion, a second portion and a third portion, and the first portion of each connecting lead is electrically connected to a first bonding electrode. The electrode carrier plate is arranged on the non-display surface and provided thereon with the second bonding electrodes arranged side by side at intervals, and each second bonding electrode is electrically connected to a third portion of a connecting lead.

Abstract: An alternating electric field-driven gallium nitride (GaN)-based nano-light-emitting diode (nanoLED) structure with an electric field enhancement effect is provided. The GaN-based nanoLED structure forms a nanopillar structure that runs through an indium tin oxide (ITO) layer, a p-type GaN layer, a multiple quantum well (MQW) active layer and an n-type GaN layer and reaches a GaN buffer layer; and the nanopillar structure has a cross-sectional area that is smallest at the MQW active layer and gradually increases towards two ends of a nanopillar, forming a pillar structure with a thin middle and two thick ends. The shape of the GaN-based nanopillar improves the electric field strength within the QW layer in the alternating electric field environment and increases the current density in the QW region of the nanopillar structure under current driving, forming strong electric field gain and current gain, thereby improving the luminous efficiency of the device.

Abstract: Provided are a link path processing method and device. A source cell may send a resource configuration request for requesting resource configuration information to a target cell. The source cell may receive a resource configuration response fed back by the target cell. The source cell may send a target cell link addition request for establishing a link path between the UE and the target cell to a user equipment (UE). The target cell link addition request may carry the resource configuration information. The resource configuration information may carry at least one of: a periodicity factor of a configuration resource, a periodicity granularity of the configuration resource, or a periodicity length of the configuration resource. The configuration information can be used for configuring a resource related to semi-persistent scheduling (SPS) or configured grant (CG) of the UE.

Abstract: The present invention belongs to the field of nanomedicine, and provides a DC biomimetic membrane nanoparticle loaded with an NIR-II AIE dye, a preparation method therefor and use thereof. The DC biomimetic membrane nanoparticle loaded with the NIR-II AIE dye comprises a DC membrane and an NIR-II AIE dye loaded therein, wherein the NIR-II AIE dye has photothermal characteristics. The DC biomimetic membrane nanoparticle loaded with the NIR-II AIE dye provided by the present invention not only solves the problem that the NIR-II AIE dye is poor in water solubility and limited in fluorescence imaging, but also increases the enrichment efficiency of the NIR-II AIE dye coated by the DC membrane at a tumor site and successfully activates the activity of T cells in vivo.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: A Y-shaped packer includes a supporting part, fixedly sleeved on the outer wall of the inner barrel; a plugging part having an inner end part connected with the outer wall of the supporting part, and an outer end part tilted upward so that an angle between the plugging part and the supporting part is an acute angle; an expansion seal connected with the supporting part. The expansion seal is located above the plugging part. The Y-shaped packer is arranged in an annular gap between an outer barrel and an inner barrel. Through the combination of the supporting part arranged obliquely and the expansion seal arranged above the supporting part, the invention-shaped packer can realize the effect of secondary sealing on the gap between the outer barrel and the inner barrel.

Abstract: An embodiment phase change material switch may include a first phase change material element, a second phase change material element, a first conductor electrically connected to a first end of each of the first phase change material element and the second phase change material element such that the first conductor is configured as a first terminal of an electrical circuit having a parallel configuration, a second conductor electrically connected to a second end of each of the first phase change material element and the second phase change material element such that the second conductor is configured as a second terminal of the electrical circuit having the parallel configuration, and a heating device coupled to the first phase change material element and to the second phase change material element and configured to supply a heat pulse to the first phase change material element and to the second phase change material element.

Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.

Abstract: The present invention discloses a one-step integrally-formed bamboo sleeper. For the one-step integrally-formed bamboo sleeper, a bamboo unit is used as a raw material, to be dried and modified at the temperature of 110-180° C., and then subject to adhesive dipping, adhesive throwing, solidification, dopamine solution treatment, anti-mildew and/or anti-corrosion and/or anti-insect treatment, and fastening, to obtain the one-step integrally-formed bamboo sleeper with a density of 0.9-1.5 g/cm3. The present invention further provides a preparation method for the foregoing bamboo sleeper. The bamboo sleeper prepared in the present invention has a suitable elastic modulus, and applicable for ballasted tracks of railways and urban rail transit systems.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Abstract: A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.

Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a bond pad structure extends to a columnar structure with a high via density. For example, an interconnect structure is on a frontside of a substrate and comprises a first bond wire, a second bond wire, and bond vias forming the columnar structure. The bond vias extend from the first bond wire to the second bond wire. The bond pad structure is inset into a backside of the substrate, opposite the frontside, and extends to the first bond wire. A projection of the first or second bond wire onto a plane parallel to a top surface of the substrate has a first area, and a projection of the bond vias onto the plane has a second area that is 10% or more of the first area, such that via density is high.