Abstract: An odd-order low-pass filter is disclosed for being interposed between a home telephone wiring network and a POTS, or voice-band, device to separate voice-band signals from higher frequency signals, such as ADSL signals and home networking signals. In one embodiment, the filter includes a pair of coupled inductors separated by a capacitor to isolate the POTS device from DSL signals. Each coupled inductor includes a pair of inductor windings wrapped about an inductor core. A resistive element positioned in parallel with each of the windings reduces interference between resonant xDSL signals and operation of an associated caller ID device.

Abstract: A combination modem including at least one line connector that is configured for coupling to a transmission medium, analog modem logic that is capable of performing analog modem communications via the transmission medium, digital modem logic that is capable of performing digital modem communications via the transmission medium, a bus interface that enables communication with a computer via an expansion bus of the computer, and processing logic. In this manner a single modem expansion card supports both analog and digital modem technologies using only one slot of an expansion bus of the computer. The analog modem logic may support 56K technologies, such as K56Flex™, V.90, etc., or any combination thereof. The digital modem logic may be according to any type of xDSL, such as ADSL, or U-ADSL, etc. The modem may operate as an analog modem, a digital modem, or as both at the same time with or without a POTS splitter.

Abstract: An odd-order low-pass microfilter is disclosed for being interposed between a home telephone wiring network and a POTS, or voice-band, device to separate voice-band signals from higher frequency signals, such as ADSL signals and home networking signals. The filter topology is substantially symmetric so that the filter is reversible in that either end of the filter may be directly coupled to the home telephone wiring network without impairing high frequency signal performance or the filter characteristic of the filter. In one embodiment, the filter is a three-pole filter with a single capacitor disposed between a pair of coupled inductors. Each of the coupled inductors advantageously has an interwinding capacitance over about 100 pF to improve the filter frequency response without increasing the cost of the filter. In another embodiment, the filter is a reversible three-pole filter with a single capacitor disposed between first and second pairs of uncoupled, or discrete, inductors.

Abstract: A combination x digital subscriber line (xDSL) and analog modem including a computer bus interface, codecs, an analog front end (AFE) for xDSL communications coupled to a plain old telephone service (POTS) line and a direct access arrangement (DAA) for analog communications also coupled to the POTS line. The modem is designed on a peripheral component interconnect (PCI) card. Generally, ±12, 5 and 3.3 volts are available for PCI components. Traditionally, the AFEs for non-PCI modems were designed to operate on ±12 volts for differential POTS line driving. For differential POTS line driving, the AFE typically requires a regulated voltage. However, ±12 volts supplied to PCI cards are typically not as well regulated as the 5 and 3.3 volts, and therefore the ±12 volts is generally unsuitable for PCI modem AFE design. Furthermore, in computers that operate in different power management modes, ±12 volts may not be available to the PCI card while 5 and/or 3.

Abstract: An interface for personal communications systems is described which provides rapid identification of a caller and limited access based on a variety of parameters obtained from caller identification information encoded by the telephone company. The incoming telephone call information is compared to a preprogrammed access matrix to determine if the caller is authorized to access the personal communications system connected to the interface. A telephone call screening method and apparatus which incorporates the encoded caller identification is also described.

Abstract: An interface for modems is described which provides rapid identification of a caller and limited access based on a variety of parameters obtained from caller identification information encoded by the telephone company. A line reversal detector is incorporated to signal when the caller identification information is available for reception. A two stage detection system is used to eliminate false signaling of line reversals and discriminate line reversals from ringing and other noise signals.

Abstract: An apparatus and method for combining video signals from multiple users in a continuous presence video conferencing system. Video signals are received from each of a number of different system users. The signals include input frames each having a number of different groups-of-blocks (GOBs). The GOBs correspond to hierarchically organized video data and header information. The input frame GOBs are used to form a composite output video signal suitable for transmission to each of the system users. An output frame of the composite output signal incorporates at least one of the GOBs from the input frames of each of the users and less than all of the GOBs from the input frame of at least one of the users. The resulting output video signal provides flexible continuous presence video conferencing in which video signals from multiple users may be simultaneously displayed to all users in a selected divided-screen format.

Abstract: An interface for modems is described which provides rapid identification of a caller and limited access based on a variety of parameters obtained from caller identification information encoded by the telephone company. The incoming telephone call information is compared to a preprogrammed access matrix to determine if the caller is authorized to access the modem connected to the interface. A telephone call screening method and apparatus which incorporates the encoded caller identification is also described. Finally, a method and apparatus for a telephone database for statistical accounting is described.

Abstract: Four QCIF video input signals generated by participants in a multiparty video conference are combined in the coded domain to produce a merged CIF video output signal. When the CIF video output signal is transmitted back to each party's video terminal, a combined 2.times.2 image is displayed. A video signal combiner (700) combines the input video signals in the coded domain by time-division multiplexing the inputs at the GOB level. In order to maintain frame synchronization between the inputs which may be arriving at different frame repetition rates, the combiner stores the inputs in buffers (706-709) and processes (710) the temporal reference (TR) numbers associated with each frame in each input before merging the GOBs from each input in accordance with the processed TR number. Specifically, the TR of each input is offset by an initial TR number associated with each input and determined at turn-on. The offset TR in each input is then mapped onto a scale of TR numbers that is common to each input.

Abstract: A variable-length codeword encoder is disclosed which produces 8-bit output segments for storage in a buffer (23) for subsequent transmission over a transmission channel (24). The encoder includes two memory tables (15, 16), which produce in response to each input symbol to be encoded, a variable-length codeword and an a codeword length. An accumulator (31, 33) accumulates, modulo-8, the successive codeword lengths, producing a carry signal during any clock cycle in which eight or more bits codeword bits are accumulated. At each clock cycle, the variable-length codeword is input to the parallel inputs of a cross bar shift control circuit (30). This shift control circuit produces a 16-bit output in which the input word is embedded.

Abstract: Method and system for high order conditional entropy coding utilizing an incremental-tree-extension technique to design a conditional tree for the coding. For complexity reduction, code table reduction and non-uniform quantization of conditioning symbols or pixels is provided. A pattern matching technique is provided for fast conditioning state extraction, and a multistage pipelined structure is provided to handle the case of a large number of conditioning pixels. Using the complexity reduction techniques and the hardware structures, it is possible to implement practical high order conditional entropy codecs using current low-cost VLSI (Very Large Scale Integration) technology.

Abstract: A variable-length decoder is disclosed which includes a decoder part (101) and an interface part (102). The decoder part includes two decoder latches (110 and 111) which store consecutive sequences of bits, which are each equal in length to the maximum-length codeword. A decoder barrel shifter (109) provides an output decoding window of a subsequence of bits in the two latches equal in length to the maximum-length codeword. This subsequence is supplied to a memory device (116) which provides a corresponding decoded codeword output and codeword-length output for each subsequence that begins with the first bit of a variable-length to be decoded. At each clock cycle, the same subsequence is supplied to the input of the first decoder latch and the decoder barrel shifter is shifted by the codeword-length of the previous word so that the decoder barrel shifter output subsequence always begins with the first bit of the word to be decoded. The interface part supplies the second decoder latch.

Abstract: A variable-length decoder is disclosed in which a received variable-word-length encoded bit stream is input to a buffer (102) and read out in parallel sequences equal in length to the maximum length codeword. These sequences are read into cascaded latches (105, 107). The cascaded sequences in both latches are input to a barrel shifter (109) which provides from its multi-bit input, a sliding decoding window to a table-lookup memory device (112). A control signal directly shifts the position of the decoding window of the barrel shifter as each codeword is detected. To detect each codeword, the initial bits in the decoding window are compared with the codeword entries in the table-lookup memory. When a codeword is detected, the corresponding stored codeword length is accumulated (120) with previously accumulated codeword lengths to produce the control signal which directly shifts the decoding window by the number of bits in the just decoded word.

Abstract: This processor is capable of real time processing of blocks of video pixel or other two-dimensional data to yield the two-dimensional Discrete Cosine Transform (DCT) thereof. The processor can be used as part of a video bandwidth or image compression system. The circuitry comprises a first one-dimensional DCT processor which simultaneously computes an entire row or column of vector inner products by using distributed arthmetic and using decimation-in-frequency to reduce the amount of memory capacity (ROM) required. Partial sums may also be used to further reduce ROM size. The one-dimensional transformed matrix from the first processor is stored in a transposition memory and the transpose of the stored matrix is applied to a second one-dimensional DCT processor of similar circuitry which computes the desired two-dimensional DCT of the input data matrix.