Abstract: The present disclosure provides a phage for lysing Burkholderia gladioli and use thereof, and belongs to the technical field of phages. The phage for lysing Burkholderia gladioli provided by the present disclosure is Burkholderia gladioli phage vB_BglM_WTB with an accession number of CCTCC M 2023525, which is a novel phage. The phage provided by the present disclosure has a strong lytic effect on the Burkholderia gladioli with higher temperature tolerance and wider acid-base tolerance range and effectively kills the Burkholderia gladioli on food surface, providing a new strategy for controlling the Burkholderia gladioli in food processing and environment.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

Abstract: An embodiment provides a stator core including a plurality of first single teeth, a plurality of second single teeth and coils. The teeth are I-shaped and each have a long side, a short side, a connection portion and a wire-accommodating slot located on the sides of the connection portion. The coils are wound around the connection portions and accommodated in the wire-accommodating slots. The stator core is an annular element formed by splicing first single teeth and second single teeth in sequence in a staggered manner into a circle, and winding modes of the coils on the first single teeth and the second single teeth are different, so that the contour of the coils located on the outer side of the wire-accommodating slots of the first single teeth is different from the contour of the coils located on the outer side of the wire-accommodating slots of the second single teeth.

Abstract: A high-frequency connector includes a plurality of connection terminal groups, at least one first metal part, a plurality of second metal parts and an insulating shell. Each connection terminal group includes a male terminal and a female terminal, the male terminal is in contact with the female terminal to transmit signals, and the connection terminal groups are arranged along a first direction; the at least one first metal part extends along the first direction; the second metal parts are disposed between the plurality of connection terminal groups and extend along a second direction, in which each second metal part includes at least two metal pieces, and the at least two metal pieces are not connected to each other; the insulating shell carries the second metal parts, so that the at least one first metal part and the second metal parts are not in contact with each other.

Abstract: Disclosed are systems, methods, and structures employing a distributed fiber optic sensing (DFOS)/distributed acoustic sensing (DAS) system operating as an underwater wireless acoustic antenna in which an optical fiber sensor cable serves as a distributed acoustic antenna that receives multiple data from transmitters using an optical interrogator. Sensing channels, in the form of acoustic-antenna-array systems are located near transmitters taking advantage of the fact that these channels are automatically synchronized. The sensing channels may also be manually selected from software controlling the interrogator, and acoustic repeaters may be introduced as one data transmission mechanism. Acoustic tata transmission using an orthogonal frequency division multiplexed (OFDM) signal is demonstrated as a cure for data transmission using a DAS, such as multipath fading impacting bit error rate (BER) and limitations in acoustic transmission bandwidth.

Abstract: A display panel includes a substrate, first bonding electrodes, connecting leads, an electrode carrier plate and second bonding electrodes. The substrate includes a display surface, a non-display surface, and a selected side face. The display surface includes a first bonding area, and the non-display surface includes a second bonding area. The first bonding electrodes are arranged side by side at the intervals in the first bonding area. The connecting leads are arranged side by side at intervals, each connecting lead includes a first portion, a second portion and a third portion, and the first portion of each connecting lead is electrically connected to a first bonding electrode. The electrode carrier plate is arranged on the non-display surface and provided thereon with the second bonding electrodes arranged side by side at intervals, and each second bonding electrode is electrically connected to a third portion of a connecting lead.

Abstract: A quantum memory device includes: a waveguide configured to spatially confine paths of photons therein; a memory cell that includes a micro-ring resonator (MRR), a frequency tuner, and a quantum memory material portion, wherein the MRR includes a first segment that is parallel to a segment of the waveguide, wherein the frequency tuner is configured to modulate a photon resonance frequency in the MRR by modifying an effective refractive index within, or around, a second segment of the MRR, and wherein the quantum memory material portion includes a quantum memory material having a ground state and an excitation state that stores photons therein and located within or on a third segment of the MRR; and a control circuit configured to modulate the photon resonance wavelength in the MRR during a first step of a photon capture operation to match a predefined wavelength, and to generate captured photons in the MRR.

Abstract: Disclosed is an unsupported hydrogenation catalyst, its preparation and application thereof. The unsupported hydrogenation catalyst is composed of a complex formed by bonding a metal central atom or central ion with an organic ligand through coordination bond, wherein the metal is selected from the group consisting of Group VB metals, Group VIB metals, Group VIII metals, Group IB metals or combinations thereof that have a hydrogenation activity. The organic ligand comprises a hydrocarbyl moiety and a coordinating group, and forms a coordination bond with the metal central atom or central ion through an oxygen atom. The unsupported hydrogenation catalyst can be used for hydrogenation reaction of hydrocarbons, and has high oil solubility, dispersibility and hydrogenation activity.

Abstract: A device includes first nanostructures over a substrate; second nanostructures over the substrate, wherein the first nanostructures are laterally separated from the second nanostructures by an isolation structure between the first nanostructures and the second nanostructures; a first gate structure around each first nanostructure and around each second nanostructure, wherein the first gate structure extends over the isolation structure; third nanostructures over the substrate; and a second gate structure around each third nanostructure, wherein the second gate structure is separated from the first gate structure by a dielectric wall.

Abstract: Systems and methods for performing the dynamic anomaly localization of utility pole aerial/suspended/supported wires/cables by distributed fiber optic sensing. In sharp contrast to the prior art, our inventive systems and methods according to aspects of the present disclosure advantageously identify a “location region” on a utility pole supporting an affected wire/cable, thereby permitting the identification and reporting of service personnel that are uniquely responsible for responding to such anomalous condition(s).

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: Aspects of the present disclosure describe distributed fiber optic sensor systems, methods, and structures that advantageously enable/provide for the proper placement/assignment of sensors in the DFOS network to provide for high reliability, fault tolerant operation that survives multiple fiber failures.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure also includes a gate structure including a first portion wrapping around the first nanostructures and a second portion wrapping around the second nanostructures. The semiconductor structure also includes a dielectric feature sandwiched between the first portion and the second portion of the gate structure. In addition, the dielectric feature includes a bottom portion and a top portion over the bottom portion, and the top portion of the dielectric feature includes a shell layer and a core portion surrounded by the shell layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a functional cell region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region including a first cutting feature and a first contact rail in the first cutting feature. The semiconductor structure also includes a first power rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell and including a second cutting feature and second contact rail in the second cutting feature. The semiconductor structure also includes an insulating strip extending from the first cutting feature to the second cutting feature in a first direction.

Abstract: A method of generating a layout diagram of a semiconductor device includes populating a conductive layer M(h) with segment patterns representing corresponding conductive segments in the semiconductor device. The segment patterns including first and second power grid (PG) patterns and first routing patterns, where h is an integer and h?1. Arranging long axes of the first and second PG patterns and the first routing patterns to extend in a first direction. Arranging the first and second PG patterns to be separated, relative to a second direction, by a PG gap having a midpoint. The second direction being substantially perpendicular to the first direction. Distributing the first routing patterns between the first and second PG patterns and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Abstract: A method of making a semiconductor device includes manufacturing an active area fin extending in a first direction over a substrate, wherein the active area fin comprises a source region, a drain region, and a channel region between the source region and the drain region. The method includes manufacturing an isolation structure next to the active area fin. The method includes manufacturing isolating fins next to the active area fin and over the isolation structure. The method includes trimming the isolating fins in first fin regions adjacent to the channel regions of the active area fin. The method includes depositing a gate electrode material against the first fin region and the gate dielectric in the channel region.

Abstract: The present invention relates to a transgenic soybean event CAL16 and its detection method thereof. The transgenic soybean event CAL16 is obtained by inserting an exogenous gene (i.e., T-DNA) between the 3? end shown in SEQ ID NO:27 and the 5? end shown in SEQ ID NO:28 of the soybean genome chromosome 18. The transgenic soybean plant CAL16 of the present invention exhibits good resistance to lepidopteran insects and good tolerance to the herbicide glyphosate, without affecting yield. Furthermore, the detection method enables accurate and rapid identification of whether a biological sample contains the DNA molecule of the transgenic soybean event CAL16.

Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes channel layers, a mask structure, a gate structure and a source/drain pattern. The channel layers are stacked vertically apart along a first direction over a substrate. The mask structure is disposed over and apart from the channel layers along the first direction. The gate structure laterally extends along a second direction perpendicular to the first direction disposed, wherein the gate structure wraps around the channel layers and laterally surround the mask structure. The source/drain pattern is in contact with the channel layers.