Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

Abstract: A system and method for determining a critical suspension speed of an impeller in a solid-liquid stirred tank belongs to the technical field of critical speed determination. A relationship is established between a voltage of a measurement electrode and a solid-liquid suspension state to avoid the problems of strong subjectivity and large deviation appearing in existing critical suspension speed determination based on empirical formulas and human eye observation. An electrode voltage ratio is taken as a determination criterion, which is only related to a spatial density of solid particles in a liquid phase.

Abstract: An optical component driving mechanism is provided, including a holder, a fixed portion, a driving assembly, and a first circuit assembly. The holder is used to connect the optical component. The holder is movable relative to the fixed portion. The driving assembly is used to drive the holder to move relative to the fixed portion. The first circuit assembly is fixedly disposed on the holder. The first circuit assembly is electrically connected to the driving assembly.

Abstract: The application relates to a method for manufacturing an electronic device, and in particular, to a method for manufacturing an electronic device with a carrier substrate. The method includes: providing a carrier, forming a first base layer on the carrier; and forming working units on the first base layer. The working units are spaced apart from one another.

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

Abstract: A package structure and a formation method are provided. The method includes forming a capacitor element over a first chip structure and forming a dielectric layer over the capacitor element. The method also includes forming a conductive bonding structure in the dielectric layer. A top surface of the conductive bonding structure is substantially coplanar with a top surface of the dielectric layer. The conductive bonding structure penetrates through the capacitor element and is electrically connected to the capacitor element. The method further includes bonding a second chip structure to the dielectric layer and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding.

Abstract: A method of forming a semiconductor device includes removing a light-sensitive material from a workpiece utilizing polarized electromagnetic radiation and annealing features on the workpiece utilizing electromagnetic radiation polarized in a different direction than the polarized electromagnetic radiation utilized to remove the light-sensitive material. In some embodiments, the electromagnetic radiation used to anneal the features on the workpiece is not polarized. In some described embodiments, light-sensitive material removed from the workpiece is exhausted from the chamber in which the light-sensitive removal process is carried out before it can deposit on surfaces of the chamber.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.

Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.

Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

Abstract: The present disclosure provides a photomask. The photomask includes a plurality of pattern areas and a training area. Each of the pattern areas is defined by a respective boundary, and a first pattern area of the pattern areas includes a first mask feature. The training area is adjacent to a boundary of the first pattern area, and includes a first training feature. The first training feature is comparable to the first mask feature.

Abstract: A temperature measuring apparatus for measuring a temperature of a substrate is described. A light emitting source that emits light signals such as laser pulses are applied to the substrate. A detector on the other side of the light emitting source receives the reflected laser pulses. The detector further receives emission signals associated with temperature or energy density that is radiated from the surface of the substrate. The temperature measuring apparatus determines the temperature of the substrate during a thermal process using the received laser pulses and the emission signals. To improve the signal to noise ratio of the reflected laser pulses, a polarizer may be used to polarize the laser pulses to have a S polarization. The angle in which the polarized laser pulses are applied towards the substrate may also be controlled to enhance the signal to noise ratio at the detector's end.

Abstract: A method of forming a semiconductor device includes removing a light-sensitive material from a workpiece utilizing polarized electromagnetic radiation and annealing features on the workpiece utilizing electromagnetic radiation polarized in a different direction than the polarized electromagnetic radiation utilized to remove the light-sensitive material. In some embodiments, the electromagnetic radiation used to anneal the features on the workpiece is not polarized. In some described embodiments, light-sensitive material removed from the workpiece is exhausted from the chamber in which the light-sensitive removal process is carried out before it can deposit on surfaces of the chamber.

Abstract: Systems and methods for compressing and querying data for real-time analytics. The system can receive log data and generate an intermediate representation by parsing a log template and variables from the log data into a columnar format. The method includes generating a compressed intermediate representation associated with an index type and storing the compressed intermediate representation in the columnar format based on the index type. The method includes receiving a search query and analyzing the search query to identify a user defined function. The method includes parsing the search query to convert the search query into one or more predicates that satisfy the search query. The method includes filtering the compressed log data based on the one or more predicates and providing a query result.

Abstract: A pressure sensor comprises a polysilicon sensing membrane. The pressure sensor further includes one or more polysilicon electrodes disposed over a silicon substrate. The sensor also includes one or more polysilicon routing layers that electrically connects electrodes of the one or more polysilicon electrodes to one another, wherein the polysilicon sensing membrane deforms responsive to a stimuli and changes a capacitance between the polysilicon sensing membrane and the one or more polysilicon electrodes. The sensor also includes one or more vacuum cavities positioned between the polysilicon sensing membrane and the one or more polysilicon electrodes.

Abstract: A method includes depositing a passivation layer on a substrate; depositing and patterning a first polysilicon layer on the passivation layer; depositing and patterning a first oxide layer on the first polysilicon layer forming a patterned first oxide layer; depositing and patterning a second polysilicon layer on the patterned first oxide layer. A portion of the second polysilicon layer directly contacts a portion of the first polysilicon layer. A portion of the patterned second polysilicon layer corresponds to a bottom electrode. A second oxide layer is deposited on the patterned second polysilicon layer and on an exposed portion of the patterned first oxide layer. A portion of the second oxide layer corresponding to a sensing cavity is etched, exposing the bottom electrode. Another substrate is bonded to the second oxide layer enclosing the sensing cavity. A top electrode is disposed within the another substrate and positioned over the bottom electrode.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures suspended over a substrate and multiple second semiconductor nanostructures suspended over the substrate. The semiconductor device structure also includes a dielectric fin between the first semiconductor nanostructures and the second semiconductor nanostructures. The semiconductor device structure further includes a metal gate stack wrapped around the dielectric fin, the first semiconductor nanostructures and the second semiconductor nanostructures. The metal gate stack has a gate dielectric layer and a gate electrode, and the gate dielectric layer extends along a sidewall and a topmost surface of the dielectric fin.

Abstract: A synchronous backlight device and an operation method thereof are provided. The synchronous backlight device includes a pulse width modulation (PWM) control circuit and a backlight driving circuit. The PWM control circuit receives the video sync information from a video processing circuit and generates a PWM control signal. Wherein, the video sync information defines a plurality of video frame periods, the PWM control circuit at least divides each of the video frame periods into a first period and a second period, the lengths of the first periods of the video frame periods are equal to one another. The frequency of the PWM control signal in the first periods is different from the frequency of the PWM control signal in the second periods. The backlight driving circuit drives the backlight source of a display panel in accordance with the PWM control signal.