Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and an isolation structure surrounding the semiconductor fin. A protruding portion of the semiconductor fin protrudes from a top surface of the isolation structure. The semiconductor device structure further includes an embedded epitaxial structure adjacent to a first side surface of the protruding portion of the semiconductor fin.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and an isolation structure surrounding the semiconductor fin. A protruding portion of the semiconductor fin protrudes from a top surface of the isolation structure. The semiconductor device structure further includes an embedded epitaxial structure adjacent to a first side surface of the protruding portion of the semiconductor fin.

Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a fin-shaped structure extending lengthwise along a first direction. The fin-shaped structure includes a stack of semiconductor layers arranged one over another along a second direction perpendicular to the first direction. The device also includes a first source/drain feature of a first dopant type on the fin-shaped structure and spaced away from the stack of semiconductor layers. The device further includes a second source/drain feature of a second dopant type on the fin-shaped structure over the first source/drain feature along the second direction and connected to the stack of semiconductor layers. The second dopant type is different from the first dopant type. Furthermore, the device additionally includes an isolation feature interposing between the first source/drain feature and the second source/drain features.

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a fin-shaped structure extending lengthwise along a first direction. The fin-shaped structure includes a stack of semiconductor layers arranged one over another along a second direction perpendicular to the first direction. The device also includes a first source/drain feature of a first dopant type on the fin-shaped structure and spaced away from the stack of semiconductor layers. The device further includes a second source/drain feature of a second dopant type on the fin-shaped structure over the first source/drain feature along the second direction and connected to the stack of semiconductor layers. The second dopant type is different from the first dopant type. Furthermore, the device additionally includes an isolation feature interposing between the first source/drain feature and the second source/drain features.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

Abstract: A method includes forming a stack of channel layers and sacrificial layers over a substrate, patterning the stack to form a fin-shape structure, and recessing a portion of the fin-shape structure to form a recess. A top surface of the substrate under the recess is covered at least by a bottommost sacrificial layer of the stack. The method also includes forming inner spacers on terminal ends of the sacrificial layers that are above the bottommost sacrificial layer, depositing an undoped layer in the recess, and forming a doped epitaxial feature over the undoped layer. The undoped layer covers terminal ends of a bottommost channel layer of the stack. The doped epitaxial feature covers terminal ends of the channel layers that are above the bottommost channel layer.

Abstract: A method includes providing a structure having a substrate, fins and an isolation structure over the substrate, wherein each fin includes first and second semiconductor layers alternatingly stacked. The method further includes depositing a first dielectric layer over top and sidewalls of the fins and over a top surface of the isolation structure; depositing a second dielectric layer over the first dielectric layer; and etching back the first and the second dielectric layers such that they remain on the top surface of the isolation structure and are removed from the top and sidewalls of the fins. The method further includes forming dummy gate stacks, gate spacers, source and drain trenches, and inner spacers, wherein the first and the second dielectric layers remain on the top surface of the isolation structure.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and multiple inner spacers. Each of the inner spacers is between the gate stack and the source/drain epitaxial structure. The semiconductor device structure further includes an isolation structure between the semiconductor fin and the source/drain epitaxial structure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first and second semiconductor layers are alternately stacked over a substrate, is formed, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers are laterally etched in the source/drain space, a first insulating layer is formed on a sidewall of the source/drain space, the first insulating layer is partially etched, thereby forming a first bottom spacer at a bottom of the source/drain space, a second insulating layer is formed on the sidewall of the source/drain space, the second insulating layer is partially etched, thereby forming inner spacers on end faces of the first semiconductor layers and leaving a part of the second insulating layer as a second bottom spacer at the bottom of the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space.

Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.