Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region. Each of the plurality of buffer layers may have an average thickness in a range of about 2 ? to about 30 ?.

Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins with a first gate pitch and second gate structures engaging the second fins with a second gate pitch smaller than the first gate pitch. The semiconductor structure also includes first epitaxial semiconductor features partially embedded in the first fins and adjacent the first gate structures and second epitaxial semiconductor features partially embedded in the second fins and adjacent the second gate structures. A bottom surface of the first epitaxial semiconductor features is lower than a bottom surface of the second epitaxial semiconductor features.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.

Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch that is smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins, second gate structures engaging the second fins, first epitaxial semiconductor features adjacent the first gate structures, and second epitaxial semiconductor features adjacent the second gate structures. The first epitaxial semiconductor features are partially embedded in the first fins at a first depth, and the second epitaxial semiconductor features are partially embedded in the second fins at a second depth that is smaller than the first depth.

Abstract: A semiconductor device includes a semiconductor substrate, an n-type fin field effect transistor. The n-type fin field effect transistor includes a fin structure, a gate stack, and a source/drain region. The gate stack includes a gate dielectric and a gate electrode. The gate dielectric is disposed in between the fin structure and the gate electrode. The source/drain region includes an epitaxial structure and an epitaxy coat covering the epitaxial structure. The epitaxial structure is made of a material having a lattice constant larger than a channel region. The epitaxy coat is made of a material having a lattice constant lower than the channel region.

Abstract: A semiconductor component includes a substrate having a dense zone and a less-dense zone, at least one first FinFET device disposed on the dense zone, and at least one second FinFET device disposed on the less-dense zone, in which a width of a first source/drain region of the first FinFET device is smaller than a width of a second source/drain region of the second FinFET device.

Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch that is smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins, second gate structures engaging the second fins, first epitaxial semiconductor features adjacent the first gate structures, and second epitaxial semiconductor features adjacent the second gate structures. The first epitaxial semiconductor features are partially embedded in the first fins at a first depth, and the second epitaxial semiconductor features are partially embedded in the second fins at a second depth that is smaller than the first depth.

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region. Each of the plurality of buffer layers may have an average thickness in a range of about 2 ? to about 30 ?.

Abstract: A semiconductor structure includes a first region. The first region includes at least three first gate structures separate one from another and adjacent to each other and at least three second gate structures separate one from another and adjacent to each other. The first gate structures are further away from each other than the second gate structures. The first region further includes first epitaxial semiconductor features proximate the first gate structures and second epitaxial semiconductor features proximate the second gate structures. A first distance from the first epitaxial semiconductor features to the respective first gate structures is smaller than a second distance from the second epitaxial semiconductor features to the respective second gate structures.

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

Abstract: A semiconductor structure includes a first region. The first region includes at least three first gate structures separate one from another and adjacent to each other and at least three second gate structures separate one from another and adjacent to each other. The first gate structures are further away from each other than the second gate structures. The first region further includes first epitaxial semiconductor features proximate the first gate structures and second epitaxial semiconductor features proximate the second gate structures. A first distance from the first epitaxial semiconductor features to the respective first gate structures is smaller than a second distance from the second epitaxial semiconductor features to the respective second gate structures.

Abstract: A semiconductor structure includes a substrate, first gate structures and second gate structures over the substrate, third epitaxial semiconductor features proximate the first gate structures, and fourth epitaxial semiconductor features proximate the second gate structures. The first gate structures have a greater pitch than the second gate structures. The third and fourth epitaxial semiconductor features are at least partially embedded in the substrate. A first proximity of the third epitaxial semiconductor features to the respective first gate structures is smaller than a second proximity of the fourth epitaxial semiconductor features to the respective second gate structures. In an embodiment, a first depth of the third epitaxial semiconductor features embedded into the substrate is greater than a second depth of the fourth epitaxial semiconductor features embedded into the substrate.

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure. The first fin structure and the second fin structure are both disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction in plan view. A first void is formed in the source/drain structure.

Abstract: A semiconductor device includes a semiconductor substrate, an n-type fin field effect transistor. The n-type fin field effect transistor includes a fin structure, a gate stack, and a source/drain region. The gate stack includes a gate dielectric and a gate electrode. The gate dielectric is disposed in between the fin structure and the gate electrode. The source/drain region includes an epitaxial structure and an epitaxy coat covering the epitaxial structure. The epitaxial structure is made of a material having a lattice constant larger than a channel region. The epitaxy coat is made of a material having a lattice constant lower than the channel region.

Abstract: A semiconductor component includes a substrate having a dense zone and a less-dense zone, at least one first FinFET device disposed on the dense zone, and at least one second FinFET device disposed on the less-dense zone, in which a width of a first source/drain region of the first FinFET device is smaller than a width of a second source/drain region of the second FinFET device.

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure. The first fin structure and the second fin structure are both disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction in plan view. A first void is formed in the source/drain structure.