Patents by Inventor Ting-Ying SHEN

Ting-Ying SHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230110795
    Abstract: An integrated circuit and an electronic device, and provides an integrated circuit having better area efficiency. The integrated circuit may be a resistive random access memory, which includes a plurality of resistive memory cells arranged in row and column directions; each resistive memory cell includes a resistive switching unit and a switch unit coupled to the resistive switching unit; the resistive switching units in the column direction are respectively coupled to corresponding source lines; the source lines include first source lines and second source lines; and the first source lines and the second source lines are located on different interconnect layers.
    Type: Application
    Filed: November 27, 2020
    Publication date: April 13, 2023
    Applicant: XIAMEN INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE CO., LTD.
    Inventors: Ting Ying SHEN, Qi XIANG
  • Patent number: 11329222
    Abstract: A resistive random access memory (RRAM) and its manufacturing method are provided. The RRAM includes a substrate having an array region and a peripheral region. A plurality of memory cells and a gap-filling dielectric layer overlying the memory cells are located on the substrate and in the array region. A buffer layer only in the array region covers the gap-filling dielectric layer, and its material layer is different from that of the gap-filling dielectric layer. A first low-k dielectric layer is only located in the peripheral region, and its material is different from that of the buffer layer. A dielectric constant of the first low-k dielectric layer is less than 3. A top surface of the first low-k dielectric layer is coplanar with that of the buffer layer. A first conductive plug passes through the buffer layer and the gap-filling dielectric layer and contacts one of the memory cells.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 10, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Ting-Ying Shen
  • Patent number: 11258011
    Abstract: An RRAM structure and its manufacturing method are provided. The RRAM structure includes a bottom electrode layer, a resistance switching layer, and an implantation control layer sequentially formed on a substrate. The resistance switching layer includes a conductive filament confined region and an outer region surrounding the conductive filament confined region. The RRAM structure includes a protective layer and a top electrode layer. The protective layer conformally covers the bottom electrode layer, the resistance switching layer, and the implantation control layer and has a first opening. The top electrode layer is located on the implantation control layer, and a portion of the top electrode layer is filled into the first opening. The position of the top electrode layer corresponds to that of the conductive filament confined region, and the top surface of the top electrode layer is higher than that of the protective layer.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: February 22, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Bo-Lun Wu, Po-Yen Hsu, Ting-Ying Shen, Meng-Hung Lin
  • Patent number: 11024802
    Abstract: Provided is a method of fabricating a resistive memory including forming a first electrode and a second electrode opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer between the variable resistance layer and the second electrode; and forming a protection layer at least covering sidewalls of the oxygen exchange layer.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 1, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
  • Patent number: 10978336
    Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer and a through hole passing through the first dielectric layer over a substrate; forming a plurality of dummy contacts in the through hole; forming a plurality of first dummy wires on the plurality of dummy contacts; filling a second dielectric layer between the plurality of first dummy wires, wherein the second dielectric layer has a first air gap; removing the dummy contacts and the first dummy wires to expose the through hole, thereby forming a first wiring trench over the through hole; and forming a contact and a first wire in the through hole and the first wiring trench.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Cheng-Hui Tu, Chi-Ching Liu, Ting-Ying Shen, Yen-De Lee, Ping-Kun Wang
  • Patent number: 10950789
    Abstract: A resistive random access memory structure includes a semiconductor substrate, a transistor, a bottom electrode, a plurality of top electrodes, and a resistive-switching layer. The transistor is disposed over the semiconductor substrate. The bottom electrode is disposed over the semiconductor substrate and is electrically connected to a drain region of the transistor. The plurality of top electrodes is disposed along a sidewall of the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the plurality of top electrodes.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 16, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Bo-Lun Wu, Yi-Hsiu Chen, Ting-Ying Shen, Po-Yen Hsu
  • Publication number: 20210005812
    Abstract: An RRAM structure and its manufacturing method are provided. The RRAM structure includes a bottom electrode layer, a resistance switching layer, and an implantation control layer sequentially formed on a substrate. The resistance switching layer includes a conductive filament confined region and an outer region surrounding the conductive filament confined region. The RRAM structure includes a protective layer and a top electrode layer. The protective layer conformally covers the bottom electrode layer, the resistance switching layer, and the implantation control layer and has a first opening. The top electrode layer is located on the implantation control layer, and a portion of the top electrode layer is filled into the first opening. The position of the top electrode layer corresponds to that of the conductive filament confined region, and the top surface of the top electrode layer is higher than that of the protective layer.
    Type: Application
    Filed: June 26, 2020
    Publication date: January 7, 2021
    Inventors: Bo-Lun WU, Po-Yen HSU, Ting-Ying SHEN, Meng-Hung LIN
  • Publication number: 20200381620
    Abstract: A resistive random access memory structure includes a semiconductor substrate, a transistor, a bottom electrode, a plurality of top electrodes, and a resistive-switching layer. The transistor is disposed over the semiconductor substrate. The bottom electrode is disposed over the semiconductor substrate and is electrically connected to a drain region of the transistor. The plurality of top electrodes is disposed along a sidewall of the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the plurality of top electrodes.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Bo-Lun WU, Yi-Hsiu CHEN, Ting-Ying SHEN, Po-Yen HSU
  • Patent number: 10840299
    Abstract: An RRAM circuit includes a first RRAM cell, a second RRAM cell, a first transistor, and a second transistor. The first RRAM cell is coupled between a first bit line and a first node. The second RRAM cell is coupled between a second bit line and the first node. The first transistor includes a first gate terminal, a first drain terminal, and a first source terminal. The first gate terminal is coupled to a first word line, the first drain terminal is coupled to the first node, and the first source terminal is coupled to a first source line. The second gate terminal is coupled to the first word line, the second drain terminal is coupled to the first node, and the second source terminal is coupled to a second source line.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 17, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chia-Ming Liu, Ting-Ying Shen, Ming-Che Lin
  • Publication number: 20200321521
    Abstract: A resistive random access memory (RRAM) and its manufacturing method are provided. The RRAM includes a substrate having an array region and a peripheral region. A plurality of memory cells and a gap-filling dielectric layer overlying the memory cells are located on the substrate and in the array region. A buffer layer only in the array region covers the gap-filling dielectric layer, and its material layer is different from that of the gap-filling dielectric layer. A first low-k dielectric layer is only located in the peripheral region, and its material is different from that of the buffer layer. A dielectric constant of the first low-k dielectric layer is less than 3. A top surface of the first low-k dielectric layer is coplanar with that of the buffer layer. A first conductive plug passes through the buffer layer and the gap-filling dielectric layer and contacts one of the memory cells.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 8, 2020
    Inventors: Po-Yen HSU, Bo-Lun WU, Ting-Ying SHEN
  • Publication number: 20200266239
    Abstract: An RRAM circuit includes a first RRAM cell, a second RRAM cell, a first transistor, and a second transistor. The first RRAM cell is coupled between a first bit line and a first node. The second RRAM cell is coupled between a second bit line and the first node. The first transistor includes a first gate terminal, a first drain terminal, and a first source terminal. The first gate terminal is coupled to a first word line, the first drain terminal is coupled to the first node, and the first source terminal is coupled to a first source line. The second gate terminal is coupled to the first word line, the second drain terminal is coupled to the first node, and the second source terminal is coupled to a second source line.
    Type: Application
    Filed: September 3, 2019
    Publication date: August 20, 2020
    Inventors: Chia-Ming LIU, Ting-Ying SHEN, Ming-Che LIN
  • Publication number: 20200235001
    Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer and a through hole passing through the first dielectric layer over a substrate; forming a plurality of dummy contacts in the through hole; forming a plurality of first dummy wires on the plurality of dummy contacts; filling a second dielectric layer between the plurality of first dummy wires, wherein the second dielectric layer has a first air gap; removing the dummy contacts and the first dummy wires to expose the through hole, thereby forming a first wiring trench over the through hole; and forming a contact and a first wire in the through hole and the first wiring trench.
    Type: Application
    Filed: December 5, 2019
    Publication date: July 23, 2020
    Inventors: Cheng-Hui TU, Chi-Ching LIU, Ting-Ying SHEN, Yen-De LEE, Ping-Kun WANG
  • Patent number: 10593877
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 17, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Po-Yen Hsu, Yi-Hsiu Chen, Ting-Ying Shen, Bo-Lun Wu, Meng-Hung Lin, Chia-Hua Ho, Ming-Che Lin
  • Publication number: 20200083446
    Abstract: Provided is a method of fabricating a resistive memory including forming a first electrode and a second electrode opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer between the variable resistance layer and the second electrode; and forming a protection layer at least covering sidewalls of the oxygen exchange layer.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
  • Patent number: 10522755
    Abstract: Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: December 31, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
  • Patent number: 10340450
    Abstract: A resistive random access memory (RRAM) structure and its forming method are provided, which includes an interlayer dielectric layer on a substrate. The interlayer dielectric layer is a dielectrics including oxygen. The RRAM structure also includes an oxygen-diffusion barrier layer on the interlayer dielectric layer, and a bottom electrode layer on the oxygen-diffusion barrier layer. The bottom electrode layer includes a first electrode layer, a first oxygen-rich layer on the first electrode layer, and a second electrode layer on the first oxygen-rich layer. The RRAM structure also includes a resistance switching layer on the bottom electrode layer, and a top electrode layer on the resistance switching layer.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 2, 2019
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Po-Yen Hsu, Chih-Cheng Fu, Ting-Ying Shen
  • Publication number: 20180269389
    Abstract: A resistive random access memory (RRAM) structure and its forming method are provided, which includes an interlayer dielectric layer on a substrate. The interlayer dielectric layer is a dielectrics including oxygen. The RRAM structure also includes an oxygen-diffusion barrier layer on the interlayer dielectric layer, and a bottom electrode layer on the oxygen-diffusion barrier layer. The bottom electrode layer includes a first electrode layer, a first oxygen-rich layer on the first electrode layer, and a second electrode layer on the first oxygen-rich layer. The RRAM structure also includes a resistance switching layer on the bottom electrode layer, and a top electrode layer on the resistance switching layer.
    Type: Application
    Filed: July 26, 2017
    Publication date: September 20, 2018
    Inventors: Po-Yen HSU, Chih-Cheng FU, Ting-Ying SHEN
  • Publication number: 20180233665
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.
    Type: Application
    Filed: April 10, 2018
    Publication date: August 16, 2018
    Applicant: Winbond Electronics Corp.
    Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Po-Yen Hsu, Yi-Hsiu Chen, Ting-Ying Shen, Bo-Lun Wu, Meng-Hung Lin, Chia-Hua Ho, Ming-Che Lin
  • Patent number: 9972779
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: May 15, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Po-Yen Hsu, Yi-Hsiu Chen, Ting-Ying Shen, Bo-Lun Wu, Meng-Hung Lin
  • Patent number: 9960349
    Abstract: A resistive random-access memory structure and a method for fabricating a resistive random-access memory structure are described. A first dielectric layer is formed on a substrate. A plurality of bottom electrodes are independently embedded in the first dielectric layer. A transition metal oxide layer covers the plurality of bottom electrodes and extends onto a portion of the first dielectric layer. The minimum distance between the bottom electrode and a sidewall of the transition metal oxide layer is a first distance. The first distance is in a range of 10 nm to 200 ?m. A top electrode is formed on the transition metal oxide layer.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: May 1, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Yi-Hsiu Chen, Ming-Hung Hsieh, Po-Yen Hsu, Ting-Ying Shen