Patents by Inventor Ting-Ying SHEN
Ting-Ying SHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9960349Abstract: A resistive random-access memory structure and a method for fabricating a resistive random-access memory structure are described. A first dielectric layer is formed on a substrate. A plurality of bottom electrodes are independently embedded in the first dielectric layer. A transition metal oxide layer covers the plurality of bottom electrodes and extends onto a portion of the first dielectric layer. The minimum distance between the bottom electrode and a sidewall of the transition metal oxide layer is a first distance. The first distance is in a range of 10 nm to 200 ?m. A top electrode is formed on the transition metal oxide layer.Type: GrantFiled: March 3, 2017Date of Patent: May 1, 2018Assignee: Winbond Electronics Corp.Inventors: Yi-Hsiu Chen, Ming-Hung Hsieh, Po-Yen Hsu, Ting-Ying Shen
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Patent number: 9812641Abstract: The invention provides a non-volatile memory device and methods for fabricating the same. The non-volatile memory device includes a non-volatile memory cell including a first transistor and a second transistor disposed on a substrate. The first and second transistors commonly use a first source region. A first gate of the first transistor and a second gate of the second transistor are different portions of a word line. First and second resistive switching elements are coupled to a first drain region of the first transistor and a second drain region of the second transistor. A first source line is coupled to the source region. First and second bit lines are coupled to the first and second resistive switching elements. The first source line, the first and second bit lines belong to a metal layer and are parallel to each other.Type: GrantFiled: September 29, 2014Date of Patent: November 7, 2017Assignee: Winbond Electronics Corp.Inventors: Hsiu-Han Liao, Ting-Ying Shen
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Patent number: 9773842Abstract: Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.Type: GrantFiled: August 8, 2016Date of Patent: September 26, 2017Assignee: Winbond Electronics Corp.Inventors: Tso-Hua Hung, Kao-Tsair Tsai, Hsaio-Yu Lin, Bo-Lun Wu, Ting-Ying Shen
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Publication number: 20170256711Abstract: A resistive random-access memory structure and a method for fabricating a resistive random-access memory structure are described. A first dielectric layer is formed on a substrate. A plurality of bottom electrodes are independently embedded in the first dielectric layer. A transition metal oxide layer covers the plurality of bottom electrodes and extends onto a portion of the first dielectric layer. The minimum distance between the bottom electrode and a sidewall of the transition metal oxide layer is a first distance. The first distance is in a range of 10 nm to 200 ?m. A top electrode is formed on the transition metal oxide layer.Type: ApplicationFiled: March 3, 2017Publication date: September 7, 2017Inventors: Yi-Hsiu CHEN, Ming-Hung HSIEH, Po-Yen HSU, Ting-Ying SHEN
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Publication number: 20170186814Abstract: Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.Type: ApplicationFiled: August 8, 2016Publication date: June 29, 2017Inventors: Tso-Hua HUNG, Kao-Tsair TSAI, Hsaio-Yu LIN, Bo-Lun WU, Ting-Ying SHEN
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Publication number: 20170170394Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Po-Yen Hsu, Yi-Hsiu Chen, Ting-Ying Shen, Bo-Lun Wu, Meng-Hung Lin
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Patent number: 9666570Abstract: The invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate, a capacitor, a protection device, a first metal interconnect, and a second metal interconnect. The capacitor is located on the substrate of a first region. The protection device is located in the substrate of a second region. The capacitor includes a plurality of bottom electrodes, a top electrode, and a capacitor dielectric layer. The top electrode has a first portion and a second portion, wherein the second portion is extended to the second region. The capacitor dielectric layer is located between the bottom electrodes and the top electrode. The first metal interconnect is located between the capacitor and the substrate. The second metal interconnect is located between the second portion of the top electrode and the protection device. The top electrode is electrically connected to the protection device through the second metal interconnect.Type: GrantFiled: October 21, 2015Date of Patent: May 30, 2017Assignee: Winbond Electronics Corp.Inventors: Bo-Lun Wu, Chia-Hua Ho, Ting-Ying Shen, Meng-Hung Lin
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Publication number: 20170125673Abstract: Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.Type: ApplicationFiled: March 9, 2016Publication date: May 4, 2017Inventors: Po-Yen Hsu, Ting-Ying Shen, Chia-Hua Ho, Chih-Cheng Fu, Frederick Chen
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Publication number: 20170018709Abstract: The invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate, a capacitor, a protection device, a first metal interconnect, and a second metal interconnect. The capacitor is located on the substrate of a first region. The protection device is located in the substrate of a second region. The capacitor includes a plurality of bottom electrodes, a top electrode, and a capacitor dielectric layer. The top electrode has a first portion and a second portion, wherein the second portion is extended to the second region. The capacitor dielectric layer is located between the bottom electrodes and the top electrode. The first metal interconnect is located between the capacitor and the substrate. The second metal interconnect is located between the second portion of the top electrode and the protection device. The top electrode is electrically connected to the protection device through the second metal interconnect.Type: ApplicationFiled: October 21, 2015Publication date: January 19, 2017Inventors: Bo-Lun Wu, Chia-Hua Ho, Ting-Ying Shen, Meng-Hung Lin
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Publication number: 20160155505Abstract: A resistive memory and a repairing method of the resistive memory are provided. Steps of the repairing method includes: operating a plurality of set-reset cycles on the resistive memory; detecting whether the resistive memory encounters an over-set issue after the set-reset cycles are operated; if the resistive memory encounters the over-set issue, executing an enhanced reset programming on the resistive memory. Here, the enhanced reset programming is executed by applying an enhanced reset voltage on the resistive memory during an enhanced reset time period. A product of the enhanced reset voltage and the enhanced reset time period is larger than a product of a reset voltage and a reset time period.Type: ApplicationFiled: June 3, 2015Publication date: June 2, 2016Inventors: Meng-Hung Lin, Bo-Lun Wu, Ting-Ying Shen
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Patent number: 9349451Abstract: A resistive memory and a repairing method of the resistive memory are provided. Steps of the repairing method includes: operating a plurality of set-reset cycles on the resistive memory; detecting whether the resistive memory encounters an over-set issue after the set-reset cycles are operated; if the resistive memory encounters the over-set issue, executing an enhanced reset programming on the resistive memory. Here, the enhanced reset programming is executed by applying an enhanced reset voltage on the resistive memory during an enhanced reset time period. A product of the enhanced reset voltage and the enhanced reset time period is larger than a product of a reset voltage and a reset time period.Type: GrantFiled: June 3, 2015Date of Patent: May 24, 2016Assignee: Winbond Electronics Corp.Inventors: Meng-Hung Lin, Bo-Lun Wu, Ting-Ying Shen
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Patent number: 9166160Abstract: Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.Type: GrantFiled: September 10, 2014Date of Patent: October 20, 2015Assignee: Winbond Electronics Corp.Inventors: Chia-Hua Ho, Shuo-Che Chang, Hsiu-Han Liao, Po-Yen Hsu, Meng-Hung Lin, Bo-Lun Wu, Ting-Ying Shen
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Publication number: 20150287914Abstract: Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.Type: ApplicationFiled: September 10, 2014Publication date: October 8, 2015Inventors: Chia-Hua Ho, Shuo-Che Chang, Hsiu-Han Liao, Po-Yen Hsu, Meng-Hung Lin, Bo-Lun Wu, Ting-Ying Shen
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Publication number: 20150280121Abstract: The invention provides a non-volatile memory device and methods for fabricating the same. The non-volatile memory device includes a non-volatile memory cell including a first transistor and a second transistor disposed on a substrate. The first and second transistors commonly use a first source region. A first gate of the first transistor and a second gate of the second transistor are different portions of a word line. First and second resistive switching elements are coupled to a first drain region of the first transistor and a second drain region of the second transistor. A first source line is coupled to the source region. First and second bit lines are coupled to the first and second resistive switching elements. The first source line, the first and second bit lines belong to a metal layer and are parallel to each other.Type: ApplicationFiled: September 29, 2014Publication date: October 1, 2015Inventors: Hsiu-Han LIAO, Ting-Ying SHEN
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Publication number: 20150214480Abstract: The disclosure provides a method for fabricating a resistive random-access memory, including: providing a substrate; forming an inter-layer dielectric layer over the substrate; forming a stop layer over the inter-layer dielectric layer; forming an opening through the stop layer and the inter-layer dielectric layer; forming a bottom electrode in the opening, wherein the bottom electrode is coplanar with the stop layer; depositing a dielectric layer over the bottom electrode and the stop layer; depositing a top electrode material over the dielectric layer; and patterning the top electrode material and the dielectric layer to define a top electrode and an inter-electrode dielectric layer under the top electrode, wherein the top electrode has a second surface opposite to a first surface of the bottom electrode, arid the second surface has a greater area than the first surface.Type: ApplicationFiled: January 28, 2014Publication date: July 30, 2015Applicant: Winbond Electronics Corp.Inventors: Po-Yen HSU, Ting-Ying SHEN, Ming-Chung CHIANG