Abstract: A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.

Abstract: A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.

Abstract: A method includes reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method further includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track. The method further includes adjusting a position of the cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

Abstract: A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.

Abstract: An integrated circuit includes a set of active regions, a first contact, a set of gates, a first and second conductive line and a first and second via. The set of active regions extends in a first direction, and is on a first level. The first contact extends in a second direction, is on a second level, and overlaps at least a first active region. The set of gates extends in the second direction, overlaps the set of active regions, and is on a third level. The first conductive line and the second conductive line extend in the first direction, overlap the first contact, and are on a fourth level. The first via electrically couples the first contact and the first conductive line together. The second via electrically couples the first contact and the second conductive line together.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

Abstract: A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

Abstract: A detection device including a substrate, a conductive pad, a conductive line, a photoelectric element, and an insulating layer is provided. The substrate includes a first region and a second region surrounding the first region. The conductive pad is disposed on the substrate and is located in the second region. The conductive line is disposed on the substrate and extends from the first region to the second region. The conductive line is coupled with the conductive pad. The photoelectric element is disposed on the substrate and is located in the first region. The photoelectric element is coupled to the conductive line. The insulating layer is disposed on the photoelectric element and extends from the first region to the second region. The insulating layer has a groove, and the groove is located in the second region. A manufacturing method of a detection device is also provided.

Abstract: A method includes a first set of active areas extending in a first direction and separated from each other along a second direction in a cell; first and second gate s that cross the first set of active areas along the second direction, the first gate being shared by a first transistor of a first type and a second transistor of a second type and the second gate being shared by a third transistor of the first type and a fourth transistor of the second type; and a set of conductive lines arranged in three metal tracks in the cell and coupling at least one of terminals of the first to fourth transistors to another one of the terminals of the first to fourth transistor. The first transistor is turned off to electrically disconnect a source/drain terminal of the first transistor from a source/drain terminal of the fourth transistor.

Abstract: Aan integrating system for evaluating and managing cultivation and targeted adoption includes a cultivating adoption evaluating and managing system, a profit returning module, and a contract terminating, rescinding and assigning module; the cultivating adoption evaluating and managing system includes, an adoption confirming system, a cultivating data and harvesting database, a contract database; the adoption confirming system includes, an adoption reporting evaluating procedure module, a contract concluding procedure module; the adoption reporting evaluating procedure module is connected to the adoption buying proposing module; with the system, an automatic solution is provided to the adoption contract, the procedure of the contract drafting to the contract signing can be processed online for establishing the filing operation; the purchasing price in the market and the profit statuses of both parties can be obtained in any desired time for the investing party and the cultivating party.

Abstract: A water quality monitoring and maintaining system includes a water quality monitoring instrument, a process system and a water quality treating module. The water quality monitoring instrument is used for collecting a plurality of water quality data of a monitored water in a monitored environment. The process system is used for processing an error correcting operation and a storing operation for the plurality of water quality data collected by the water quality monitoring instrument, thereby establishing a water quality data model. The water quality treating module is used for adjusting the plurality of water quality data of the monitored environment according to the water quality data model.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: A method of generating an IC layout diagram includes positioning a cell in the IC layout diagram relative to a first metal layer cut region alignment pattern and overlapping the cell with a first metal layer cut region. The cell includes a first metal layer region corresponding to one of a first or second mask set, the first metal layer cut region alignment pattern includes a sub-pattern corresponding to the one of the first or second mask set, and the first metal layer cut region corresponds to the sub-pattern.

Abstract: A filler cell region (in a semiconductor device) includes: gate segments, a majority of first ends of which substantially align with a first reference line that parallel and proximal to a top boundary of the filler cell region, and a majority of second ends of which substantially align with a second reference line that is parallel and proximal to a bottom boundary of the filler cell region. First and second gate segments extend continuously across the filler cell region; and third & fourth and fifth & sixth gate segments are correspondingly coaxial and separated by corresponding gate-gaps. Relative to the first direction: a first end of the first gate segment extends to the top boundary of the filler cell region; and a second end of the second gate segment extends to the bottom boundary of the filler cell region.

Abstract: A method of manufacturing a transmission gate includes overlying a first active area with a first metal zero segment, the first active area including first and second PMOS transistors, overlying a second active area with a second metal zero segment, the second active area including first and second NMOS transistors, and configuring the first and second PMOS transistors and the first and second NMOS transistors as a transmission gate by forming three conductive paths. At least one of the conductive paths includes a first conductive segment perpendicular to the first and second metal zero segments, and the first and second metal zero segments have a first offset distance corresponding to three times a metal zero pitch.

Abstract: An integrated circuit is disclosure. The integrated circuit includes a first pair of power rails, a set of conductive lines arranged in the first layer parallel to the first pair of power rails, a first set of active areas. The integrated circuit further includes a first gate arranged along the second direction, between the first pair of power rails, and crossing the first set of active areas in a layout view, wherein the first gate is configured to be shared by a first transistor of a first type and a second transistor of a second type; and a second gate and a third gate, in which the second gate is configured to be a control terminal of a third transistor, and the third gate is configured to be a control terminal of a fourth transistor which is coupled to the control terminal of the third transistor.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: Provided herein are gas permeable membranes comprising an amine-containing selective layer on top of a gas permeable polymer support as well as methods of making and using thereof. The membranes are useful for the separation of CO2 from N2-containing gases.

Abstract: A semiconductor cell structure includes four pairs of conductive segments, a first gate-strip, and a second gate-strip. A first conductive segment is configured to have a first supply voltage, and a second conductive segment is configured to have a second supply voltage. Each of the first gate-strip and the second gate-strip intersects an active zone over a channel region of a transistor. The first gate-strip is conductively connected to the second conductive segment. The semiconductor cell structure also includes a first dummy gate-strip and a second dummy gate-strip. The first dummy gate-strip separates from the first gate-strip by one CPP. The second dummy gate-strip separates from the second gate-strip by one CPP. The first gate-strip and the second gate-strip are separated from each other by two CPPs. The dummy gate-strip and the second dummy gate-strip are separated from each other by four CPPs.