Patents by Inventor Ting-Yu Yeh
Ting-Yu Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929340Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.Type: GrantFiled: August 4, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Yu Yeh, Chun-Hua Chang, Fong-Yuan Chang, Jyh Chwen Frank Lee
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Publication number: 20240021442Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.Type: ApplicationFiled: August 1, 2023Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
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Publication number: 20240021560Abstract: A semiconductor device includes a first connector, a second connector, and a redistribution structure disposed between the first connector and the second connector. The redistribution structure includes a first connection tree electrically connecting the first connector to the second connector. The first connection tree includes a plurality of first conductive pads disposed in a plurality of respective levels, and a plurality of first via structures each disposed between adjacent ones of the plurality of first conductive pads. Any lateral end of each of the plurality of first conductive pads is spaced from the first connector within a first minimum pitch associated with the second connector.Type: ApplicationFiled: July 14, 2022Publication date: January 18, 2024Applicant: Taiwan Semicondutor Manufacturing Company, Ltd.Inventors: Ting-Yu Yeh, Han-Hsiang Huang, Chun-Hsien Wen, Chih-Wei Chang
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Publication number: 20230386985Abstract: A semiconductor structure includes a solder resist layer disposed on a circuit substrate and partially covering contact pads of the circuit substrate, and external terminals disposed on the solder resist layer and extending through the solder resist layer to land on the contact pads. The external terminals include a first external terminal and a second external terminal which have different heights. A first interface between the first external terminal and corresponding one of the contact pads underlying the first external terminal is less than a second interface between the second external terminal and another corresponding one of the contact pads underlying the second external terminal.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu, Kuan-Yu Huang, Shu-Chia Hsu
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Publication number: 20230386969Abstract: Connection structures and methods of manufacture in which a conductive structure is disposed between, and in electrical contact with, pluralities of via structures. Each via structure is laterally offset from adjacent via structures to avoid stacked vias, and each via is electrically connected to at least two additional vias on a level of a semiconductor device, through conductive traces and footprints of the connection structure.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Yu Yeh, Shu-Cheng Li, Chun-Hsien Wen, Chih-Wei Chang
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Patent number: 11728238Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided.Type: GrantFiled: July 29, 2019Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu
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Publication number: 20230124804Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
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Publication number: 20230050785Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. A plurality of conductive balls is placed over a circuit substrate, where each of the conductive balls is placed over a contact area of one of a plurality of contact pads that is accessibly revealed by a patterned mask layer. The conductive balls are reflowed to form a plurality of external terminals with varying heights connected to the contact pads of the circuit substrate, where a first external terminal of the external terminals formed in a first region of the circuit substrate and a second external terminal of the external terminals formed in a second region of the circuit substrate are non-coplanar.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Yu Yeh, Ching-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu, Kuan-Yu Huang, Shu-Chia Hsu
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Patent number: 11532585Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.Type: GrantFiled: December 14, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
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Publication number: 20220336321Abstract: A manufacturing method of a semiconductor package includes the following steps. An encapsulated semiconductor package is provided on a substrate. A heat dissipation sheet is cut into a plurality of heat dissipation films. The plurality of heat dissipation films are attached on the encapsulated semiconductor package, wherein the plurality of heat dissipation films jointly cover an upper surface of the encapsulated semiconductor package. A cover lid is provided on the substrate, wherein the cover lid is in contact with the plurality of heat dissipation films.Type: ApplicationFiled: July 4, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu
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Publication number: 20220310411Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
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Publication number: 20220230981Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.Type: ApplicationFiled: August 4, 2021Publication date: July 21, 2022Inventors: Ting-Yu Yeh, Chun-Hua Chang, Fong-Yuan Chang, Jyh Chwen Frank Lee
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Patent number: 11139282Abstract: A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.Type: GrantFiled: July 26, 2018Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kuo-Chiang Ting, Tu-Hao Yu, Ting-Yu Yeh, Chia-Hao Hsu, Weiming Chris Chen, Wan-Yu Lee, Yu-Jie Su
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Publication number: 20210098408Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
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Publication number: 20210035884Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided.Type: ApplicationFiled: July 29, 2019Publication date: February 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu
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Patent number: 10867954Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.Type: GrantFiled: November 15, 2017Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
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Patent number: 10720401Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.Type: GrantFiled: September 19, 2019Date of Patent: July 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
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Publication number: 20200144155Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.Type: ApplicationFiled: December 23, 2019Publication date: May 7, 2020Inventors: TING-YU YEH, CHIA-HAO HSU, WEIMING CHRIS CHEN, KUO-CHIANG TING, TU-HAO YU, SHANG-YUN HOU
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Patent number: 10626375Abstract: The present invention describes applications and methods (1) to use bacterophage Cf and its variants to prevent and treat the citrus canker pathogen, Xanthomonas citri subsp. citri; (2) to engineer recombinant Cf phages that the infectivity is controllable without being harmful to the rest of environment; (3) to engineer and produce recombinant Cf phages with longer storage shelf life; (4) to use Cf phage as a vector for the introduction and insertion of foreign genetic material into Xanthomonas citri subsp. citri. genome; (5) to use and engineer Xp12 and Xf bacteriophages to inhibit Xanthomonas oryzae pv. oryzae, the causal agent of the rice blight disease.Type: GrantFiled: June 24, 2015Date of Patent: April 21, 2020Assignee: Auxergen, Inc.Inventor: Ting-Yu Yeh
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Publication number: 20200035655Abstract: A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.Type: ApplicationFiled: July 26, 2018Publication date: January 30, 2020Inventors: KUO-CHIANG TING, TU-HAO YU, TING-YU YEH, CHIA-HAO HSU, WEIMING CHRIS CHEN, WAN-YU LEE, YU-JIE SU