Patents by Inventor Ting-Yu Yeh

Ting-Yu Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200027851
    Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 23, 2020
    Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
  • Patent number: 10515869
    Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ting-Yu Yeh, Chia-Hao Hsu, Weiming Chris Chen, Kuo-Chiang Ting, Tu-Hao Yu, Shang-Yun Hou
  • Publication number: 20190371700
    Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.
    Type: Application
    Filed: May 29, 2018
    Publication date: December 5, 2019
    Inventors: TING-YU YEH, CHIA-HAO HSU, WEIMING CHRIS CHEN, KUO-CHIANG TING, TU-HAO YU, SHANG-YUN HOU
  • Patent number: 10304800
    Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first die disposed over the second surface of the first substrate; a plurality of first conductive bumps disposed between the first die and the first substrate; a molding disposed over the first substrate and surrounding the first die and the plurality of first conductive bumps; a second substrate disposed below the first surface of the first substrate; a plurality of second conductive bumps disposed between the first substrate and the second substrate; and a second die disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Weiming Chris Chen, Ting-Yu Yeh, Chia-Hsin Chen, Tu-Hao Yu, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
  • Publication number: 20190148329
    Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
  • Publication number: 20180374821
    Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first die disposed over the second surface of the first substrate; a plurality of first conductive bumps disposed between the first die and the first substrate; a molding disposed over the first substrate and surrounding the first die and the plurality of first conductive bumps; a second substrate disposed below the first surface of the first substrate; a plurality of second conductive bumps disposed between the first substrate and the second substrate; and a second die disposed between the first substrate and the second substrate.
    Type: Application
    Filed: November 1, 2017
    Publication date: December 27, 2018
    Inventors: WEIMING CHRIS CHEN, TING-YU YEH, CHIA-HSIN CHEN, TU-HAO YU, KUO-CHIANG TING, SHANG-YUN HOU, CHI-HSI WU
  • Publication number: 20180105801
    Abstract: The present invention describes applications and methods (1) to use bacteriophage Cf and its variants to prevent and treat the citrus canker pathogen, Xanthomonas citri subsp. citri; (2) to engineer recombinant Cf phages that the infectivity is controllable without being harmful to the rest of environment; (3) to engineer and produce recombinant Cf phages with longer storage shelf life; (4) to use Cf phage as a vector for the introduction and insertion of foreign genetic material into Xanthomonas citri subsp. citri. genome; (5) to use and engineer Xp12 and Xf bacteriophages to inhibit Xanthomonas oryzae pv. oryzae, the causal agent of the rice blight disease.
    Type: Application
    Filed: June 24, 2015
    Publication date: April 19, 2018
    Inventor: Ting-Yu YEH
  • Patent number: 9899305
    Abstract: A semiconductor package structure is disclosed. The semiconductor package structure includes: a substrate having a front surface and a back surface; a chip-on-interposer structure mounted on the front surface of the substrate; a back side stiffener mounted over the back surface of the substrate and surrounding a projection of the chip-on-interposer structure from a back surface perspective; and a plurality of conductive bumps mounted on the back surface of the substrate.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ting-Yu Yeh, Wei-Ming Chen, Yi-Chiang Sun