Abstract: Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, an apparatus includes a power detector circuit powered by a first voltage supply. At least one voltage level-shifting device is coupled to a second voltage supply and a test input is provided to the power detector circuit. An optional leakage self-control device may reduce unwanted leakage currents associated with the first supply and the second supply.

Abstract: A receiver equalization circuit includes a first output transistor having a gate coupled to an input signal. The receiver equalization circuit may also include a second output transistor having a drain coupled to a drain of the first output transistor. The receiver equalization circuit may also include a resistor coupled between a gate and a drain of the second output transistor to provide a direct current (DC) bias to the gate of the second output transistor. The receiver equalization circuit may further include a feed-through capacitor coupled between the gate of the second output transistor and an input signal source. The feed-through capacitor feeds the input signal to the gate of the second output transistor when a frequency of the input signal is above a predetermined threshold. The feed-through capacitor and the resistor define a signal gain amplification point.

Abstract: A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

Abstract: A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry.

Abstract: A system for calibrating a closed power control loop includes an adder configured to inject a test signal into an adjustable element, a first peak detector configured to determine an amplitude of the injected test signal, a second peak detector configured to determine an amplitude of a return test signal, a comparator configured to determine the difference between the injected test signal and the return test signal, and a calibration engine configured to adjust the adjustable element so that the return test signal is offset from the injected test signal by a predetermined amount.

Abstract: A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.

Abstract: A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.

Abstract: Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, an apparatus includes a power detector circuit powered by a first voltage supply. At least one voltage level-shifting device is coupled to a second voltage supply and a test input is provided to the power detector circuit. An optional leakage self-control device may reduce unwanted leakage currents associated with the first supply and the second supply.

Abstract: A system for calibrating a closed power control loop includes an adder configured to inject a test signal into an adjustable element, a first peak detector configured to determine an amplitude of the injected test signal, a second peak detector configured to determine an amplitude of a return test signal, a comparator configured to determine the difference between the injected test signal and the return test signal, and a calibration engine configured to adjust the adjustable element so that the return test signal is offset from the injected test signal by a predetermined amount.

Abstract: In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.

Abstract: A system for calibrating a closed power control loop includes an adder configured to inject a test signal into an adjustable element, a first peak detector configured to determine an amplitude of the injected test signal, a second peak detector configured to determine an amplitude of a return test signal, a comparator configured to determine the difference between the injected test signal and the return test signal, and a calibration engine configured to adjust the adjustable element so that the return test signal is offset from the injected test signal by a predetermined amount.

Abstract: A system for saturation detection, correction and recovery in a power amplifier includes a power amplifier, a closed power control loop configured to develop a power control signal (VPC), and power control circuitry configured to reduce the power control signal if the power amplifier is operating in a saturation mode.

Abstract: A closed loop power control system for a radio frequency (RF) transmitter comprises a first variable gain element located in a power control loop and configured to receive a power level signal and an inverse representation of a power control signal, a second variable gain element located in the power control loop and configured to receive an error signal and the power control signal, and a third variable gain element configured to receive an amplitude modulated (AM) signal and the power control signal, the third variable gain element having a gain characteristic configured to operate to reduce the gain applied to the AM signal when the power control signal falls below a minimum predetermined value, and to provide the AM signal as a reference signal.

Abstract: A supply voltage controlled power amplifier includes a power amplifier, a closed power control loop configured to generate a power control signal, and a voltage regulator coupled to the power control loop, the voltage regulator including a first regulator stage, a second regulator stage, and a peak detector, wherein an output of the second regulator stage is applied as a feedback signal to the first regulator stage and wherein an output of the first regulator stage is decreased to a level consistent with an output of the power amplifier and an additional operating buffer amount.

Abstract: A system for saturation detection, correction and recovery in a power amplifier includes a power amplifier, a closed power control loop configured to develop a power control signal (VPC), and power control circuitry configured to reduce the power control signal if the power amplifier is operating in a saturation mode.

Abstract: A differential radio frequency (RF) receiver includes a fully differential direct conversion receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a differential radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired receive LO signals.

Abstract: A system for saturation detection, correction and recovery in a power amplifier includes a power amplifier, a closed power control loop configured to develop a power control signal (VPC), and power control circuitry configured to reduce the power control signal if the power amplifier is operating in a saturation mode.

Abstract: A system for generating local oscillator (LO) signals for a quadrature mixer includes an oscillator configured to provide a reference frequency signal, at least one frequency divider configured to divide the reference frequency signal into three offset phase signals, a first summing circuit configured to generate two nominal 90 degree offset phase signals from the three offset phase signals, and a second summing circuit configured to generate at least two amplitude-corrected 90 degree offset-phase quadrature signals.

Abstract: A system for controlling gain in a polar loop is disclosed. Embodiments of the invention provide for a substantially constant gain tolerant of changes in supply voltage, ambient temperature, and/or manufacturing process.

Abstract: A system for compensating gain control variations in a power amplifier comprises a power control element configured to receive a power control signal and an instantaneous envelope power reference signal, an adder configured to combine the power control signal and the instantaneous envelope power reference signal to obtain a modified power level signal, and a mapping function configured to receive the modified power level signal and configured to alter a control input to a variable gain amplifier, the variable gain amplifier controlling an adjustable input to the power amplifier.