Abstract: A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifying transistor to obtain a conduction angle of less than about 180°. The dc bias circuit includes a dynamic biasing circuit for decreasing the dc bias signal provided to the amplifying transistor as the input signal to the power amplifier circuit increases. This configuration permits the amplifier circuit to operate as a linearized Class C amplifier, having a substantially linear input-output relationship similar to that of a Class B amplifier, but with increased operating efficiency.

Abstract: A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifier transistor to obtain a conduction angle of at least about 180°. The dc bias circuit includes a self-bias boosting circuit for initially decreasing and then increasing the dc bias voltage provided to a control terminal of the amplifying transistor by the dc bias circuit as the input signal provided to the power amplifier increases. The self-bias boosting circuit is extremely simple and compact in design, and permits the power amplifier circuits to operate in Class B or Class AB with improved power output characteristics.

Abstract: A capacitor structure having a first level of electrically conductive parallel lines and at least a second level of electrically conductive parallel lines disposed over the lines in the first level, the lines of the first and second levels being arranged in vertical rows. A dielectric layer is disposed between the first and second levels of conductive lines. One or more vias connect the first and second level lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. Electrically opposing nodes form the terminals of the capacitor. The parallel array of vertical capacitor plates are electrically connected to the nodes in an alternating manner so that the plates have alternating electrical polarities.

Abstract: A high-frequency amplifier circuit includes an amplifying transistor and a bias circuit coupled to the amplifying transistor. The bias circuit includes a first bias subcircuit for controlling a quiescent current in the amplifying transistor and a second bias subcircuit for independently controlling a bias impedance of the amplifying transistor. Using this configuration, it is possible to set the gain and class of operation of the amplifying transistor, while independently controlling the bias impedance of the amplifying transistor to obtain improved linearity and tuning capability as well as increased efficiency.

Abstract: A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifier transistor to obtain a conduction angle of at least about 180°. The dc bias circuit includes a dynamic bias boosting circuit for increasing the dc bias current provided to the amplifying transistor by the dc bias circuit in direct proportion to an increase in the input signal provided to the power amplifier. The bias boosting circuit permits the power amplifier circuits to operate in Class B or Class AB with improved power output characteristics and reduced power dissipation at low power levels.

Abstract: A capacitor structure having a first and at least a second conductor level of electrically conductive concentric ring-shaped lines. The conductive lines of the first and at least second levels are arranged in concentric ring-shaped stacks. A dielectric material is disposed between the first and second conductor levels and between the concentric conductive lines in each of the levels. At least one electrically conductive via electrically connects the conductive lines in each stack, thereby forming a concentric array of ring-shaped capacitor plates. The concentric array of capacitor plates are electrically connected in an alternating manner to first and second terminals of opposite polarity so that capacitance is generated between adjacent plates of the array. The capacitor structure is especially useful in deep sub-micron CMOS.

Abstract: A relaxation oscillator, such as a voltage controlled oscillator (VCO), with automatic swing control feedback which dynamically monitors the voltage swing across a capacitor and adjusts the oscillator threshold voltage, at which reversal of the polarity of the charging/discharging current occurs, to maintain the effective voltage swing at a constant level. The improved relaxation oscillator provides a very wide linear range of frequency variation versus control voltage (or current) and allows for the extendibility of linear operation to or near the maximum frequency that can be practically achieved by the oscillator circuitry.