Abstract: A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.

Abstract: A neuron circuit for use in a neural network is disclosed. The neural network includes a plurality of field effect transistors having confined channels. The sources and drains of the field effect transistors are connected in series. A plurality of input terminals for receiving a plurality of input voltages may be connected to a drain terminal of a corresponding field effect transistor. The threshold voltages of the field effect transistors can be programmed by increasing or decreasing a number of excess minority carriers in the confined channels, thereby programming the resistance presented by the field effect transistor.

Abstract: A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.

Abstract: A nanosheet field effect transistor design in which the threshold voltage is adjustable by adjusting the composition of the gate. The channel of the nanosheet field effect transistor may be composed of a III-V semiconductor material, and the gate, which may be separated from the channel by a high dielectric constant dielectric layer, may also be composed of a III-V semiconductor material. Adjusting the composition of the gate may result in a change in the affinity of the gate, in turn resulting in a change in the threshold voltage. In some embodiments the channel is composed, for example, of InxGa1-xAs, with x between 0.23 and 0.53, and the gate is composed of InAs1-yNy with y between 0.0 and 0.4, and the values of x and y may be adjusted to adjust the threshold voltage.

Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

Abstract: A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage, a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal, and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.

Abstract: An integrated circuit (IC) including a circuit block including a plurality of complementary metal oxide semiconductor field-effect transistors (CMOSFETs), and a tunnel field-effect transistor (TFET) between the circuit block and ground for power gating the circuit block.

Abstract: Multi-layer fin field effect transistor devices and methods of forming the same are provided. The devices may include a fin shaped channel structure on a substrate. The channel structure may include stressor layers stacked on the substrate and a channel layer between the stressor layers, and the stressor layers may include a semiconductor material having a wide bandgap that is sufficient to confine carriers to the channel layer and having a lattice constant different from a lattice constant of the channel layer to induce stress in the channel layer. The devices may also include source/drain regions on respective first opposing sides of the channel structure and a gate on second opposing sides of the channel structure and between the source/drain regions.

Abstract: A vertical field effect device includes a substrate and a vertical channel including InxGa1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.

Abstract: According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum VDD includes: determining an x value in InxGa1?xAs according to the BTBT leakage and the maximum VDD, and forming a channel utilizing InxGa1?xA, wherein x is not 0.53.

Abstract: A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage, a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal, and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.

Abstract: A Gate-All-Around (GAA) Field Effect Transistor (FET) can include a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, a height that is perpendicular to the horizontal direction, and a length that extends in the horizontal direction, where the width of the horizontal nanosheet conductive channel structure defines a physical channel width of the GAA FET. First and second source/drain regions can be located at opposing ends of the horizontal nanosheet conductive channel structure and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.

Abstract: A nanosheet field effect transistor design in which the threshold voltage is adjustable by adjusting the composition of the gate. The channel of the nanosheet field effect transistor may be composed of a III-V semiconductor material, and the gate, which may be separated from the channel by a high dielectric constant dielectric layer, may also be composed of a III-V semiconductor material. Adjusting the composition of the gate may result in a change in the affinity of the gate, in turn resulting in a change in the threshold voltage. In some embodiments the channel is composed, for example, of InxGa1-xAs, with x between 0.23 and 0.53, and the gate is composed of InAs1-yNy with y between 0.0 and 0.4, and the values of x and y may be adjusted to adjust the threshold voltage.

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract: A Gate-All-Around (GAA) Field Effect Transistor (FET) can include a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, a height that is perpendicular to the horizontal direction, and a length that extends in the horizontal direction, where the width of the horizontal nanosheet conductive channel structure defines a physical channel width of the GAA FET. First and second source/drain regions can be located at opposing ends of the horizontal nanosheet conductive channel structure and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.

Abstract: A bidirectional memory cell includes a write unit and a read unit. The write unit and the read unit each include an MTJ structure having a first and second pinned layers and a free layer. The first and second pinned layers are separated from the free layer by at least one tunnel barrier. The first pinned layer is electrically coupled to a first write line through a first diode. The second pinned layer is electrically connected to a second word line through a second diode. The free layer is electrically coupled to a first bit line. Additionally, the free layer of the read unit is magnetically coupled to the free layer of the write unit.

Abstract: A vertical field effect device includes a substrate and a vertical channel including InxGa1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.