Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.

Abstract: A pixel array substrate including a substrate, a plurality of pixel structures and a scan device is provided. The pixel structures are arranged on the substrate along a first direction. Each pixel structure includes a data line, an active device and a pixel electrode. The active device has a semiconductor pattern, a source electrode and a drain electrode. The source electrode and the drain electrode are electrically connected to the data line and the pixel electrode respectively. The scan device includes a first and a second scan line. The first and the second scan line extend in the first direction and are electrically connected to each other. The active devices of the pixel structures are electrically connected to the first and the second scan line. The first and the second scan line respectively overlap two different regions of the semiconductor pattern of each active device.

Abstract: A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The first semiconductor die has first conductive posts and a first protection layer laterally surrounding the first conductive posts. The second semiconductor die is embedded in the first protection layer and surrounded by the first conductive posts of the first semiconductor die, wherein the second semiconductor die includes second conductive posts. The insulating encapsulant is encapsulating the first semiconductor die and the second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected with the first conductive posts and the second conductive posts, wherein the first semiconductor die is electrically connected with the second semiconductor die through the first conductive posts, the redistribution layer and the second conductive posts.

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a conductive layer over a semiconductor substrate and forming a sacrificial layer over the conductive layer. The method also includes partially removing the sacrificial layer to form a first dummy element. The method further includes etching the conductive layer with the first dummy element as an etching mask to form a conductive line. In addition, the method includes partially removing the first dummy element to form a second dummy element over the conductive line. The method also includes forming a dielectric layer to surround the conductive line and the second dummy element and removing the second dummy element to form a via hole exposing the conductive line. The method further includes forming a conductive via in the via hole.

Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first seal ring disposed over the molding, and a second seal ring disposed below the molding. The semiconductor structure further includes a first interconnect structure disposed below the first surface of the die and a second interconnect structure disposed over the second surface and the molding. The first seal ring is disposed in the second interconnect structure and disposed over the molding, and the second seal ring is provided within the die and the first interconnect structure.

Abstract: Disclosed in some examples are methods, systems and machine-readable mediums which allow for more secure authentication attempts by implementing authentication systems with credentials that include interspersed noise symbols in positions determined by the user. These systems secure against eavesdroppers such as shoulder-surfers or man-in-the middle attacks as it is difficult for an eavesdropper to separate the noise symbols from legitimate credential symbols.

Abstract: Fluid collection systems and methods are disclosed which may utilize suction to draw fluids into containers for storage and eventual disposal. The system may utilize rigid or semi-rigid canisters to provide a chamber in which fluids may be collected under negative pressure, stored, and transported. The system may utilize disposable or reusable flexible, semi-rigid, or rigid liners for isolating fluid and liquid waste from the walls of the canister. In various embodiments, either a single canister assembly or multiple canister assemblies are mounted to a manifold, the manifold being configured to support each canister assembly and/or provide a connection to a source of suction for each canister assembly.

Abstract: A heat sink includes a base and a plurality of fins. A root of the fin is connected to the base. A heated area, a dropping pipe, and a spacing strip between the heated area and the dropping pipe are formed in the fin. A first passage and a second passage are formed between the heated area and the dropping pipe. A hydraulic diameter of a pipeline in the heated area is less than a critical dimension. A hydraulic diameter of a pipeline of the dropping pipe is greater than or equal to the critical dimension, and a pressure of liquid at an intersection of the second passage and the dropping pipe is greater than a pressure of liquid at an intersection of the second passage and the heated area.

Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.

Abstract: Disclosed are a gamma value tuning method of a display panel, which comprises the following steps: setting a preset gamma value interval according to a parameters of a display panel to be tested; acquiring a brightness value of a gray scale on the display panel to be tested; calculating a gamma value corresponding to the brightness value of the gray scale; adjusting the gamma value to the first gamma value when the gamma value is smaller than the first gamma value of the preset gamma value interval; adjusting the gamma value to the second gamma, when the second gamma value in the gamma value is larger than the preset gamma value interval.

Abstract: A semiconductor device includes a first substrate including a first surface, at least one first bonding pad disposed on the first surface, and at least one second bonding pad disposed on the first surface. The first bonding pad includes a first width, and the second bonding pad includes a second width. The second width is substantially different from the first width.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer over a first substrate, and the dielectric layer has a plurality of openings. The method also includes forming a first graphene layer in the openings and over the first dielectric layer, and forming an insulating layer in the first graphene layer. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second graphene layer in and over the second dielectric layer. A portion of the second graphene layer interfaces with a portion of the first graphene layer.

Abstract: Methods, systems, and programs provide for executing distributed transactions in a cloud storage system with a hierarchical namespace. One method includes receiving a request with operations to be executed atomically. Further, nodes are identified for executing the operations, each node having a respective clock and having at least part of a transactions table for controlling updates to entities. Each clock is one of a loosely-synchronized, a strictly-synchronized clock, a logical, or a physical clock. Additionally, the nodes process the operations, which includes setting a commit timestamp (CS) to a value of the clock in the node if the node is a first node in the processing. One node coordinates the transactions, and may be one of the nodes executing transactions. If the clock in the node is less than a current value of the CS, the node waits for the clock to reach the current value of the CS and the CS is updated.

Abstract: Aspects of the present disclosure include methods and systems for detecting light from a sample in a flow stream by multi-photon counting. Methods according to certain embodiments include irradiating a sample in a flow stream with a light source and detecting light from the sample in the flow stream and counting photons of the detected light by integrating photo-electron charge over a time interval. Methods also include irradiating a sample in a flow stream with a light source, detecting light from the sample in the flow stream and outputting a digital output signal and an analog output signal produced by the detected light. Systems for detecting light from a sample in a flow stream with a detector and counting photons by integrating photo-electron charge over a time interval are also described. Kits having a detector, a photon counter and a flow cell configured to propagate a sample in flow stream are also provided.

Abstract: Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

Abstract: A system for transmitting data over an optical communication path is configured to receive data to be encoded in a bitstream for transmission using an optical communication path and encodes the received data to obtain a bitstream. The system is further configured to determine that the bitstream includes a sequence of consecutive bits, and obtain a power level at which to transmit a portion of the bitstream based on a count of the consecutive bits in the sequence. The system may be configured to selectively activate a light source at a power level according to a modulation scheme to optically transmit the portion of the bitstream at the power level.

Abstract: Disclosed in some examples, are optical devices, systems, and machine-readable mediums that send and receive multiple streams of data across a same optical communication path (e.g., a same fiber optic fiber) with a same wavelength using different light sources transmitting at different power levels—thereby increasing the bandwidth of each optical communication path. Each light source corresponding to each stream transmits at a same frequency and on the same optical communication path using a different power level. The receiver differentiates the data for each stream by applying one or more detection models to the photon counts observed at the receiver to determine likely bit assignments for each stream.