Patents by Inventor Tobias ERLBACHER

Tobias ERLBACHER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250227940
    Abstract: Method for producing a trench capacitor structure, including the steps of providing a silicon substrate with a trench structure comprising a plurality of recesses in a main surface of the silicon substrate; forming a first silicon dioxide layer at least in the recesses of the silicon substrate; depositing a first silicon nitride layer on the first silicon dioxide layer; depositing a second silicon dioxide layer on the first silicon nitride layer by depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer; and depositing a second silicon nitride layer on the second silicon dioxide layer.
    Type: Application
    Filed: January 9, 2025
    Publication date: July 10, 2025
    Inventors: Tom BECKER, Tobias ERLBACHER
  • Publication number: 20250133810
    Abstract: A method for producing a (thick) bottom oxide in a trench structure, having the following steps: providing a substrate having at least one trench structure comprising a bottom and sidewalls; depositing a polysilicon layer on a surface of the substrate, the bottom and the sidewalls; depositing an oxide layer on the polysilicon layer; depositing a nitride layer on the oxide layer; anisotropic dry etching of the nitride layer; thermal oxidation of the polysilicon of the polysilicon layer to produce a thick oxide layer locally; and wet etching; depositing a further oxide layer on the thick oxide layer along at least the bottom and the surface or on the residual oxide along the bottom and the surface and on the sidewalls.
    Type: Application
    Filed: October 24, 2024
    Publication date: April 24, 2025
    Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Minwho LIM, Alesa FUCHS, Tobias ERLBACHER
  • Patent number: 12113096
    Abstract: In a method for producing semiconductor capacitors having different capacitance values on a common substrate, firstly a partially processed semiconductor substrate is produced as a semi-finished product with hole structures and filled with a layer sequence of a dielectric and an electrically conductive layer—independently of the semiconductor capacitors to be produced subsequently. The production of the semiconductor capacitors having different capacitance values only then takes place in a second production phase by corresponding metallization and structuring. The semiconductor capacitors are then separated along dividing regions through which different groups of holes are separated from one another during the production of the semi-finished product. The method enables a more cost-effective production of semiconductor capacitors having different capacitance values in small numbers of items in make-to-order fabrication (foundry process).
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 8, 2024
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventor: Tobias Erlbacher
  • Patent number: 11854890
    Abstract: In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: December 26, 2023
    Assignees: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V., Friedrich-Alexander-Universitaet Erlangen-Nuernberg
    Inventors: Florian Krach, Tobias Erlbacher
  • Patent number: 11742435
    Abstract: Integrated capacitor including a first electrode structure, a second electrode structure, and an interposed dielectric layer structure. The dielectric layer structure includes a layer combination having an SiO2 layer, an Si3N4 layer, and an SixNy layer. The SixNy layer includes a non-stoichiometric silicon nitride material with an increased proportion of silicon.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: August 29, 2023
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Norman Böttcher, Tobias Erlbacher
  • Patent number: 11552199
    Abstract: A high-voltage capacitor for integration into electrical power modules has a silicon layer into which an arrangement of recesses is introduced on a front face. The front face with the recesses is coated with a dielectric layer or dielectric layer sequence, wherein the recesses are filled with an electrically conductive material. The silicon layer bears a contact metallisation on the front face and the rear face for purposes of making electrical contact with the capacitor. A layer of thermal SiO2 is formed between the silicon layer and the dielectric layer or layer sequence. The dielectric layer or layer sequence has a layer thickness of ?1000 nm and is formed from a ferroelectric or anti-ferroelectric material. The proposed high-voltage capacitor features a high integration density with a high capacitance and good heat dissipation properties.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 10, 2023
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventor: Tobias Erlbacher
  • Publication number: 20210257502
    Abstract: Integrated capacitor including a first electrode structure, a second electrode structure, and an interposed dielectric layer structure. The dielectric layer structure includes a layer combination having an SiO2 layer, an Si3N4 layer, and an SixNy layer. The SixNy layer includes a non-stoichiometric silicon nitride material with an increased proportion of silicon.
    Type: Application
    Filed: April 6, 2021
    Publication date: August 19, 2021
    Inventors: Norman BÖTTCHER, Tobias ERLBACHER
  • Publication number: 20210210386
    Abstract: In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions.
    Type: Application
    Filed: March 1, 2021
    Publication date: July 8, 2021
    Inventors: Florian KRACH, Tobias ERLBACHER
  • Patent number: 10957684
    Abstract: In an electrical circuit arrangement, which is formed by an RC-snubber element monolithically integrated into a semiconductor substrate, a first capacitor and a resistor of the RC-snubber element are vertically formed in a semiconductor region of a first type of doping of the semiconductor substrate. At least one further capacitor is connected in series with the first capacitor. The further capacitor is integrated laterally with the first capacitor in a semiconductor region of a second type of doping, which adjoins the semiconductor region of the first type of doping, and by virtue of the different type of doping electrically insulates the further capacitor from the semiconductor region of the first type of doping. This circuit arrangement forms a low inductance RC-snubber element with high dielectric strength, which has high heat dissipation and integration density.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: March 23, 2021
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Tobias Erlbacher, Andreas Schletz, Gudrun Rattmann
  • Patent number: 10937696
    Abstract: In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: March 2, 2021
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Florian Krach, Tobias Erlbacher
  • Patent number: 10804421
    Abstract: The present invention relates to a UV-radiation sensor with a radiation-sensitive region of diamond, which is formed on the first face of a semiconductor substrate and with which electrical contact can be made via at least two contact electrodes. In the proposed UV-radiation sensor, the radiation-sensitive region has two differently doped regions of diamond that form a pn-junction for purposes of radiation detection. Such a UV-radiation sensor has a high sensitivity in the wavelength range ?200 nm.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 13, 2020
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventor: Tobias Erlbacher
  • Publication number: 20200168597
    Abstract: In an electrical circuit arrangement, which is formed by an RC-snubber element monolithically integrated into a semiconductor substrate, a first capacitor and a resistor of the RC-snubber element are vertically formed in a semiconductor region of a first type of doping of the semiconductor substrate. At least one further capacitor is connected in series with the first capacitor. The further capacitor is integrated laterally with the first capacitor in a semiconductor region of a second type of doping, which adjoins the semiconductor region of the first type of doping, and by virtue of the different type of doping electrically insulates the further capacitor from the semiconductor region of the first type of doping. This circuit arrangement forms a low inductance RC-snubber element with high dielectric strength, which has high heat dissipation and integration density.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 28, 2020
    Inventors: Tobias ERLBACHER, Andreas Schletz, Gudrun Rattmann
  • Patent number: 10659035
    Abstract: In a power module that has a carrier substrate with at least one unipolar semiconductor component as a power switch, the unipolar semiconductor component is configured such that a temperature rise of the semiconductor component, from a first temperature up to which the semiconductor component heats in operation at 50% full load, to a second temperature up to which the semiconductor component heats in operation at full load, is less than a temperature rise of the semiconductor component from an initial temperature at zero load to the first temperature. As a result of the reduced temperature rise between 50% and 100% full load the service life of the power module can be lengthened.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: May 19, 2020
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Tobias Erlbacher, Andreas Schletz
  • Patent number: 10530361
    Abstract: The present invention relates to an electrical circuit arrangement with an active discharge circuit including at least one electrical switching element, by means of which the circuit arrangement can be discharged in controlled manner. The circuit arrangement includes a RC snubber element with capacitor and resistor for damping voltage or current peaks in the circuit arrangement, wherein the electrical switching element is integrated in the RC snubber element and connected in parallel to the capacitor of the RC snubber. This enables the discharge circuit to be designed in a manner that is economical in terms of space and cost. The discharge circuit uses the heat sink for the RC snubber element and therefore does not need any additional heat dissipation systems.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: January 7, 2020
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Tobias Erlbacher, Stefan Matlok
  • Publication number: 20190386166
    Abstract: The present invention relates to a UV-radiation sensor with a radiation-sensitive region of diamond, which is formed on the first face of a semiconductor substrate and with which electrical contact can be made via at least two contact electrodes. In the proposed UV-radiation sensor, the radiation-sensitive region has two differently doped regions of diamond that form a pn-junction for purposes of radiation detection. Such a UV-radiation sensor has a high sensitivity in the wavelength range ?200 nm.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 19, 2019
    Inventor: Tobias Erlbacher
  • Patent number: 10325984
    Abstract: In a semiconductor switch with a monolithically integrated field effect transistor, the source or emitter region of the field effect transistor is connected via a semiconductor region and an n-doped contact region to a first electrical terminal. In the semiconductor region, a semiconductor structure with n-doped channels is formed between the n-doped contact region and the source or emitter region of the field effect transistor; the n-doped channels electrically connect the n-doped contact region with the source or emitter region of the field effect transistor and run between p-doped regions that are connected to the n-doped contact region. The semiconductor switch is suitable as a self-switching load disconnector and has low losses in the switched-on state.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 18, 2019
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Andreas Huerner, Tobias Erlbacher
  • Publication number: 20190043852
    Abstract: In a semiconductor switch with a monolithically integrated field effect transistor, the source or emitter region of the field effect transistor is connected via a semiconductor region and an n-doped contact region to a first electrical terminal. In the semiconductor region, a semiconductor structure with n-doped channels is formed between the n-doped contact region and the source or emitter region of the field effect transistor; the n-doped channels electrically connect the n-doped contact region with the source or emitter region of the field effect transistor and run between p-doped regions that are connected to the n-doped contact region. The semiconductor switch is suitable as a self-switching load disconnector and has low losses in the switched-on state.
    Type: Application
    Filed: July 30, 2018
    Publication date: February 7, 2019
    Inventors: Andreas Huerner, Tobias Erlbacher
  • Patent number: 10186734
    Abstract: A semiconductor substrate has a first doping region arranged at a surface and a second doping region adjacent to the first doping region. A p-n junction between the doping regions is at least partially arranged less than 5 ?m away from a contact area of the first doping region arranged at the substrate surface. A first contact structure is in contact with the first doping region in the contact area of the first doping region and has at least partially an electrically conductive material provided for a diffusion into the semiconductor substrate. The first contact structure is configured so that the conductive material provided for a diffusion into the substrate diffuses at least partially through the first doping region into the second doping region in case predefined trigger conditions occur. A second contact structure is in contact with the second doping region in a contact area of the second doping region.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 22, 2019
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Tobias Erlbacher, Vincent Lorentz, Reinhold Waller, Gudrun Rattmann
  • Patent number: 10141456
    Abstract: The invention disclosure describes a manufacturing method for realizing so-called JBS areas for a unipolar power diode on the basis of diamond. In this special method, an n-doped layer is applied to the typically p-doped drift region, e.g. by means of epitaxial layer growth. The applied n-doped layer is then removed again in defined areas. A photolithographic mask may be applied and the n-doped layer is removed by dry or wet chemical etching. Having structured the JBS areas, the Schottky metal is applied to the entire surface. The resulting JBS structure shields an electric field generated by an applied reverse voltage from the Schottky transition. The reverse voltage from which the Schottky transition is fully shielded can be adjusted by altering the distance between the JBS areas.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: November 27, 2018
    Assignee: Fraunhofer Gesellschaft Zur Forderung Der Angew. Forschung E.V.
    Inventors: Andreas Hürner, Tobias Erlbacher
  • Publication number: 20180108788
    Abstract: The invention disclosure describes a manufacturing method for realizing so-called JBS areas for a unipolar power diode on the basis of diamond. In this special method, an n-doped layer is applied to the typically p-doped drift region, e.g. by means of epitaxial layer growth. The applied n-doped layer is then removed again in defined areas. A photolithographic mask may be applied and the n-doped layer is removed by dry or wet chemical etching. Having structured the JBS areas, the Schottky metal is applied to the entire surface. The resulting JBS structure shields an electric field generated by an applied reverse voltage from the Schottky transition. The reverse voltage from which the Schottky transition is fully shielded can be adjusted by altering the distance between the JBS areas.
    Type: Application
    Filed: October 17, 2016
    Publication date: April 19, 2018
    Inventors: Andreas Hürner, Tobias Erlbacher