Patents by Inventor Tobias ERLBACHER
Tobias ERLBACHER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11854890Abstract: In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions.Type: GrantFiled: March 1, 2021Date of Patent: December 26, 2023Assignees: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V., Friedrich-Alexander-Universitaet Erlangen-NuernbergInventors: Florian Krach, Tobias Erlbacher
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Patent number: 11742435Abstract: Integrated capacitor including a first electrode structure, a second electrode structure, and an interposed dielectric layer structure. The dielectric layer structure includes a layer combination having an SiO2 layer, an Si3N4 layer, and an SixNy layer. The SixNy layer includes a non-stoichiometric silicon nitride material with an increased proportion of silicon.Type: GrantFiled: April 6, 2021Date of Patent: August 29, 2023Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.Inventors: Norman Böttcher, Tobias Erlbacher
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Patent number: 11552199Abstract: A high-voltage capacitor for integration into electrical power modules has a silicon layer into which an arrangement of recesses is introduced on a front face. The front face with the recesses is coated with a dielectric layer or dielectric layer sequence, wherein the recesses are filled with an electrically conductive material. The silicon layer bears a contact metallisation on the front face and the rear face for purposes of making electrical contact with the capacitor. A layer of thermal SiO2 is formed between the silicon layer and the dielectric layer or layer sequence. The dielectric layer or layer sequence has a layer thickness of ?1000 nm and is formed from a ferroelectric or anti-ferroelectric material. The proposed high-voltage capacitor features a high integration density with a high capacitance and good heat dissipation properties.Type: GrantFiled: April 15, 2019Date of Patent: January 10, 2023Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventor: Tobias Erlbacher
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Publication number: 20210257502Abstract: Integrated capacitor including a first electrode structure, a second electrode structure, and an interposed dielectric layer structure. The dielectric layer structure includes a layer combination having an SiO2 layer, an Si3N4 layer, and an SixNy layer. The SixNy layer includes a non-stoichiometric silicon nitride material with an increased proportion of silicon.Type: ApplicationFiled: April 6, 2021Publication date: August 19, 2021Inventors: Norman BÖTTCHER, Tobias ERLBACHER
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Publication number: 20210210386Abstract: In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions.Type: ApplicationFiled: March 1, 2021Publication date: July 8, 2021Inventors: Florian KRACH, Tobias ERLBACHER
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Patent number: 10957684Abstract: In an electrical circuit arrangement, which is formed by an RC-snubber element monolithically integrated into a semiconductor substrate, a first capacitor and a resistor of the RC-snubber element are vertically formed in a semiconductor region of a first type of doping of the semiconductor substrate. At least one further capacitor is connected in series with the first capacitor. The further capacitor is integrated laterally with the first capacitor in a semiconductor region of a second type of doping, which adjoins the semiconductor region of the first type of doping, and by virtue of the different type of doping electrically insulates the further capacitor from the semiconductor region of the first type of doping. This circuit arrangement forms a low inductance RC-snubber element with high dielectric strength, which has high heat dissipation and integration density.Type: GrantFiled: November 19, 2019Date of Patent: March 23, 2021Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Tobias Erlbacher, Andreas Schletz, Gudrun Rattmann
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Patent number: 10937696Abstract: In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions.Type: GrantFiled: November 24, 2015Date of Patent: March 2, 2021Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.Inventors: Florian Krach, Tobias Erlbacher
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Patent number: 10804421Abstract: The present invention relates to a UV-radiation sensor with a radiation-sensitive region of diamond, which is formed on the first face of a semiconductor substrate and with which electrical contact can be made via at least two contact electrodes. In the proposed UV-radiation sensor, the radiation-sensitive region has two differently doped regions of diamond that form a pn-junction for purposes of radiation detection. Such a UV-radiation sensor has a high sensitivity in the wavelength range ?200 nm.Type: GrantFiled: May 31, 2019Date of Patent: October 13, 2020Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventor: Tobias Erlbacher
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Publication number: 20200168597Abstract: In an electrical circuit arrangement, which is formed by an RC-snubber element monolithically integrated into a semiconductor substrate, a first capacitor and a resistor of the RC-snubber element are vertically formed in a semiconductor region of a first type of doping of the semiconductor substrate. At least one further capacitor is connected in series with the first capacitor. The further capacitor is integrated laterally with the first capacitor in a semiconductor region of a second type of doping, which adjoins the semiconductor region of the first type of doping, and by virtue of the different type of doping electrically insulates the further capacitor from the semiconductor region of the first type of doping. This circuit arrangement forms a low inductance RC-snubber element with high dielectric strength, which has high heat dissipation and integration density.Type: ApplicationFiled: November 19, 2019Publication date: May 28, 2020Inventors: Tobias ERLBACHER, Andreas Schletz, Gudrun Rattmann
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Patent number: 10659035Abstract: In a power module that has a carrier substrate with at least one unipolar semiconductor component as a power switch, the unipolar semiconductor component is configured such that a temperature rise of the semiconductor component, from a first temperature up to which the semiconductor component heats in operation at 50% full load, to a second temperature up to which the semiconductor component heats in operation at full load, is less than a temperature rise of the semiconductor component from an initial temperature at zero load to the first temperature. As a result of the reduced temperature rise between 50% and 100% full load the service life of the power module can be lengthened.Type: GrantFiled: October 1, 2019Date of Patent: May 19, 2020Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Tobias Erlbacher, Andreas Schletz
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Publication number: 20200112304Abstract: In a power module that has a carrier substrate with at least one unipolar semiconductor component as a power switch, the unipolar semiconductor component is configured such that a temperature rise of the semiconductor component, from a first temperature up to which the semiconductor component heats in operation at 50% full load, to a second temperature up to which the semiconductor component heats in operation at full load, is less than a temperature rise of the semiconductor component from an initial temperature at zero load to the first temperature. As a result of the reduced temperature rise between 50% and 100% full load the service life of the power module can be lengthened.Type: ApplicationFiled: October 1, 2019Publication date: April 9, 2020Inventors: TOBIAS ERLBACHER, ANDREAS SCHLETZ
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Publication number: 20200111864Abstract: In a method for producing semiconductor capacitors having different capacitance values on a common substrate, firstly a partially processed semiconductor substrate is produced as a semi-finished product with hole structures and filled with a layer sequence of a dielectric and an electrically conductive layer—independently of the semiconductor capacitors to be produced subsequently. The production of the semiconductor capacitors having different capacitance values only then takes place in a second production phase by corresponding metallization and structuring. The semiconductor capacitors are then separated along dividing regions through which different groups of holes are separated from one another during the production of the semi-finished product. The method enables a more cost-effective production of semiconductor capacitors having different capacitance values in small numbers of items in make-to-order fabrication (foundry process).Type: ApplicationFiled: September 27, 2019Publication date: April 9, 2020Inventor: TOBIAS ERLBACHER
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Patent number: 10530361Abstract: The present invention relates to an electrical circuit arrangement with an active discharge circuit including at least one electrical switching element, by means of which the circuit arrangement can be discharged in controlled manner. The circuit arrangement includes a RC snubber element with capacitor and resistor for damping voltage or current peaks in the circuit arrangement, wherein the electrical switching element is integrated in the RC snubber element and connected in parallel to the capacitor of the RC snubber. This enables the discharge circuit to be designed in a manner that is economical in terms of space and cost. The discharge circuit uses the heat sink for the RC snubber element and therefore does not need any additional heat dissipation systems.Type: GrantFiled: June 19, 2018Date of Patent: January 7, 2020Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Tobias Erlbacher, Stefan Matlok
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Publication number: 20190386166Abstract: The present invention relates to a UV-radiation sensor with a radiation-sensitive region of diamond, which is formed on the first face of a semiconductor substrate and with which electrical contact can be made via at least two contact electrodes. In the proposed UV-radiation sensor, the radiation-sensitive region has two differently doped regions of diamond that form a pn-junction for purposes of radiation detection. Such a UV-radiation sensor has a high sensitivity in the wavelength range ?200 nm.Type: ApplicationFiled: May 31, 2019Publication date: December 19, 2019Inventor: Tobias Erlbacher
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Publication number: 20190326449Abstract: A high-voltage capacitor for integration into electrical power modules has a silicon layer into which an arrangement of recesses is introduced on a front face. The front face with the recesses is coated with a dielectric layer or dielectric layer sequence, wherein the recesses are filled with an electrically conductive material. The silicon layer bears a contact metallisation on the front face and the rear face for purposes of making electrical contact with the capacitor. A layer of thermal SiO2 is formed between the silicon layer and the dielectric layer or layer sequence. The dielectric layer or layer sequence has a layer thickness of ?1000 nm and is formed from a ferroelectric or anti-ferroelectric material. The proposed high-voltage capacitor features a high integration density with a high capacitance and good heat dissipation properties.Type: ApplicationFiled: April 15, 2019Publication date: October 24, 2019Inventor: TOBIAS ERLBACHER
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Patent number: 10325984Abstract: In a semiconductor switch with a monolithically integrated field effect transistor, the source or emitter region of the field effect transistor is connected via a semiconductor region and an n-doped contact region to a first electrical terminal. In the semiconductor region, a semiconductor structure with n-doped channels is formed between the n-doped contact region and the source or emitter region of the field effect transistor; the n-doped channels electrically connect the n-doped contact region with the source or emitter region of the field effect transistor and run between p-doped regions that are connected to the n-doped contact region. The semiconductor switch is suitable as a self-switching load disconnector and has low losses in the switched-on state.Type: GrantFiled: July 30, 2018Date of Patent: June 18, 2019Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Andreas Huerner, Tobias Erlbacher
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Publication number: 20190043852Abstract: In a semiconductor switch with a monolithically integrated field effect transistor, the source or emitter region of the field effect transistor is connected via a semiconductor region and an n-doped contact region to a first electrical terminal. In the semiconductor region, a semiconductor structure with n-doped channels is formed between the n-doped contact region and the source or emitter region of the field effect transistor; the n-doped channels electrically connect the n-doped contact region with the source or emitter region of the field effect transistor and run between p-doped regions that are connected to the n-doped contact region. The semiconductor switch is suitable as a self-switching load disconnector and has low losses in the switched-on state.Type: ApplicationFiled: July 30, 2018Publication date: February 7, 2019Inventors: Andreas Huerner, Tobias Erlbacher
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Patent number: 10186734Abstract: A semiconductor substrate has a first doping region arranged at a surface and a second doping region adjacent to the first doping region. A p-n junction between the doping regions is at least partially arranged less than 5 ?m away from a contact area of the first doping region arranged at the substrate surface. A first contact structure is in contact with the first doping region in the contact area of the first doping region and has at least partially an electrically conductive material provided for a diffusion into the semiconductor substrate. The first contact structure is configured so that the conductive material provided for a diffusion into the substrate diffuses at least partially through the first doping region into the second doping region in case predefined trigger conditions occur. A second contact structure is in contact with the second doping region in a contact area of the second doping region.Type: GrantFiled: May 22, 2015Date of Patent: January 22, 2019Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.Inventors: Tobias Erlbacher, Vincent Lorentz, Reinhold Waller, Gudrun Rattmann
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Publication number: 20190007041Abstract: The present invention relates to an electrical circuit arrangement with an active discharge circuit including at least one electrical switching element, by means of which the circuit arrangement can be discharged in controlled manner. The circuit arrangement includes a RC snubber element with capacitor and resistor for damping voltage or current peaks in the circuit arrangement, wherein the electrical switching element is integrated in the RC snubber element and connected in parallel to the capacitor of the RC snubber. This enables the discharge circuit to be designed in a manner that is economical in terms of space and cost. The discharge circuit uses the heat sink for the RC snubber element and therefore does not need any additional heat dissipation systems.Type: ApplicationFiled: June 19, 2018Publication date: January 3, 2019Inventors: TOBIAS ERLBACHER, Stefan Matlok
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Patent number: 10141456Abstract: The invention disclosure describes a manufacturing method for realizing so-called JBS areas for a unipolar power diode on the basis of diamond. In this special method, an n-doped layer is applied to the typically p-doped drift region, e.g. by means of epitaxial layer growth. The applied n-doped layer is then removed again in defined areas. A photolithographic mask may be applied and the n-doped layer is removed by dry or wet chemical etching. Having structured the JBS areas, the Schottky metal is applied to the entire surface. The resulting JBS structure shields an electric field generated by an applied reverse voltage from the Schottky transition. The reverse voltage from which the Schottky transition is fully shielded can be adjusted by altering the distance between the JBS areas.Type: GrantFiled: October 17, 2016Date of Patent: November 27, 2018Assignee: Fraunhofer Gesellschaft Zur Forderung Der Angew. Forschung E.V.Inventors: Andreas Hürner, Tobias Erlbacher