Abstract: An optical sensor includes a pixel including a photoactive region configured to convert photons into charge carriers, a first and a second modulation gate configured to be modulated for indirect time of flight measurement, a first and a second storage node arranged on opposite sides of the photoactive region, the first and second storage nodes being configured to pin electrons generated in the photoactive region when the first or the second modulation gate is active, respectively, and a first field plate arranged next to the first storage node and a second field plate arranged next to the second storage node. The first and second field plates are configured to be supplied with a negative bias voltage such that the first and second field plates provide electrical isolation for the first or the second storage node, respectively.

Abstract: An optical sensor includes a pixel that includes: a photoactive region configured to convert photons into electrons and holes, first and second modulation gates configured to be modulated for indirect time of flight measurement, the first and second modulation gates being arranged on a front side of the pixel, first and second trenches arranged on opposite lateral sides of the photoactive region, and a first memory part arranged laterally next to the first trench and at least partially separated from the photoactive region by the first trench and a second memory part arranged laterally next to the second trench and at least partially separated from the photoactive region by the second trench, the first and second memory parts being configured to bin electrons generated in the photoactive region, and the first and second trenches are configured as reflective structures for photons in the photoactive region.

Abstract: A heteroepitaxial semiconductor device includes a seed layer including a first semiconductor material, the seed layer including a first side, an opposing second side and lateral sides connecting the first and second sides, a separation layer arranged at the first side of the seed layer, the separation layer including an aperture, a heteroepitaxial structure grown at the first side of the seed layer at least in the aperture and including a second semiconductor material, different from the first semiconductor material, and a first dielectric material layer arranged at the second side of the seed layer and covering the lateral sides of the seed layer.

Abstract: An image sensor device includes a pixel. The pixel includes a semiconductor layer having a first surface. A photodiode is formed in the semiconductor layer and is configured to generate charge carriers based on light reaching the photodiode. A storage node is formed in the semiconductor layer, the storage node being arranged so that charge carriers generated in the photodiode are transferred to the storage node. A light-shielding structure is formed in the semiconductor layer and is disposed at least between the first surface of the semiconductor layer and the storage node so as to prevent at least part of the light travelling in the semiconductor layer away from the first surface from reaching the storage node.

Abstract: Embodiments of the invention provide methods for making an integrated circuit comprising providing a substrate, forming a structured layer stack on the substrate comprising a dielectric layer located on the substrate and an oxide-free metallic layer located on the dielectric layer, wherein the metallic layer comprising a transition metal. The method further comprises oxidizing the metallic layer, thereby increasing a work function of the metallic layer. Moreover, a substrate for making an integrated circuit is described.

Abstract: A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.

Abstract: The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.

Abstract: A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.

Abstract: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.

Abstract: A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.

Abstract: Embodiments of the invention provide methods for making an integrated circuit comprising providing a substrate, forming a structured layer stack on the substrate comprising a dielectric layer located on the substrate and an oxide-free metallic layer located on the dielectric layer, wherein the metallic layer comprising a transition metal. The method further comprises oxidizing the metallic layer, thereby increasing a work function of the metallic layer. Moreover, a substrate for making an integrated circuit is described.

Abstract: An integrated circuit comprises a dielectric layer located on a substrate and an electrode located on the dielectric layer. The electrode comprises a first metallic layer located on the dielectric layer and a second metallic layer. Moreover, a method of making an integrated circuit is described.

Abstract: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.

Abstract: The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.

Abstract: The invention is related to a method of producing a semiconductor structure comprising the steps of: fabricating a gate stack structure and oxidizing at least a portion of the gate stack structure's sidewalls, wherein the step of oxidizing is carried out at a temperature below 500° C. using a process gas which comprises oxygen radicals.

Abstract: The present invention provides a fabrication method for an integrated circuit structure comprising the steps of forming a electrode layer stack (5, 6?, 7?, 8?) by sequentially depositing a polysilicon layer (5) on a gate dielectric layer (9); a contact layer (6?) composed of Ti on the polysilicon layer (5); a barrier layer (7?) composed of WN on the contact layer (6?); and a metal layer (8?) composed of W on the barrier layer (7?); wherein steps iii) and iv) are carried out as PVD steps using krypton and/or xenon as sputtering gas; and annealing the layer stack (5, 6?, 7?, 8?) in a thermal step in the temperature range of between 600 and 950° C.

Abstract: A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.

Abstract: The invention relates to a method and an apparatus for the arrangement of contact-making elements of components of an integrated circuit, a computer-readable storage medium and a program element. In the method for the arrangement of contact-making elements of components of an integrated circuit, at least one part of at least one component having a larger extent along a first course direction than along a second course direction, which is orthogonal to the first course direction, and at least one contact-making element assigned to a component having, in cross section, a larger extent along a third course direction than along a fourth course direction, which is orthogonal to the third course direction, the contact-making element is arranged with respect to the assigned component in such a way that the first course direction of the component essentially runs parallel to the third course direction of the contact-making element.

Abstract: Preferably using a positive resist, a resist ridge (20) is formed in a photosensitive resist (16) applied on a semiconductor wafer (1) above a hard mask layer (12). The resist ridge (20) serves as a mask for a subsequent implantation step (46). This makes use of an effect whereby the material of the hard mask layer (12), in a part (122) shaded by the resist ridge (20), can be etched out selectively with respect to the implanted part (121). The consequently patterned hard mask layer is used as an etching mask with respect to an underlying layer or layer stack (102–104) that is actually to be patterned. From the resist ridge (10) that has been formed as a line in the photosensitive resist (16), in a type of tone reversal, an opening (24) has been formed in the hard mask layer and a trench (26) has been formed in the layer/layer stack (102–104). According to the invention, the width (51, 52) of the resist ridge (20) is reduced by exposing the resist ridge (20) to an oxygen plasma (42).

Abstract: A plate 50 for projection lithography comprising a first opaque region 54 located at the center of the plate 50 and a second opaque region 56 formed at the outer edge 52 of the plate. The first and second opaque regions define a light transmissive annular region 58. The annular region 58 comprises a first light transmissive area 60, 62 that imparts a first phase shift to light passing therethrough and a second light transmissive area 64, 66, which imparts a second phase shift to light passing therethrough.