Abstract: Preferably using a positive resist, a resist ridge (20) is formed in a photosensitive resist (16) applied on a semiconductor wafer (1) above a hard mask layer (12). The resist ridge (20) serves as a mask for a subsequent implantation step (46). This makes use of an effect whereby the material of the hard mask layer (12), in a part (122) shaded by the resist ridge (20), can be etched out selectively with respect to the implanted part (121). The consequently patterned hard mask layer is used as an etching mask with respect to an underlying layer or layer stack (102-104) that is actually to be patterned. From the resist ridge (10) that has been formed as a line in the photosensitive resist (16), in a type of tone reversal, an opening (24) has been formed in the hard mask layer and a trench (26) has been formed in the layer/layer stack (102-104). According to the invention, the width (51, 52) of the resist ridge (20) is reduced by exposing the resist ridge (20) to an oxygen plasma (42).

Abstract: The invention relates to a method and an apparatus for the arrangement of contact-making elements of components of an integrated circuit, a computer-readable storage medium and a program element. In the method for the arrangement of contact-making elements of components of an integrated circuit, at least one part of at least one component having a larger extent along a first course direction than along a second course direction, which is orthogonal to the first course direction, and at least one contact-making element assigned to a component having, in cross section, a larger extent along a third course direction than along a fourth course direction, which is orthogonal to the third course direction, the contact-making element is arranged with respect to the assigned component in such a way that the first course direction of the component essentially runs parallel to the third course direction of the contact-making element.

Abstract: A method for electrically determining in a semiconductor wafer the location of edges of a well that underlies an insulating layer that includes forming in the wafer before forming of the well and the insulating layer a plurality of conductive stripes will that pass under the future insulating layer and extend to varying distances under the insulating layer so as to include stripes that will penetrate an edge to be located so as to form a low resistance connection thereto and stripes that will fall short of an edge to be located. From the stripes of minimum penetration that make low resistance can be determined the location of the well edges.

Abstract: A plate 50 for projection lithography comprising a first opaque region 54 located at the center of the plate 50 and a second opaque region 56 formed at the outer edge 52 of the plate. The first and second opaque regions define a light transmissive annular region 58. The annular region 58 comprises a first light transmissive area 60, 62 that imparts a first phase shift to light passing therethrough and a second light transmissive area 64, 66, which imparts a second phase shift to light passing therethrough.

Abstract: Disclosed is an optical lithographic mask having one or more dummy patterns, each said dummy pattern having a masked area of said optical lithographic mask separated from one or more feature masked areas on said optical lithographic mask by an unmasked region of width d, wherein said width d is selected to substantially minimize an average deviation between the dimensions of said feature masked areas and corresponding features etched out upon a semiconductor surface utilizing said optical lithographic mask.

Abstract: A method for electrically determining in a semiconductor wafer the location of edges of a well that underlies an insulating layer that includes forming in the wafer before forming of the well and the insulating layer a plurality of conductive stripes will that pass under the future insulating layer and extend to varying distances under the insulating layer so as to include stripes that will penetrate an edge to be located so as to form a low resistance connection thereto and stripes that will fall short of an edge to be located. From the stripes of minimum penetration that make low resistance can be determined the location of the well edges.

Abstract: An alternating phase shift mask (400) and method of manufacturing thereof including assist edges (450) and (452) surrounding a main phase edge (420). Assist edges (450) and (452) improve the resolution of the alternating phase shift mask (400), thus enabling the patterning of smaller size features on a semiconductor wafer.

Abstract: Method and apparatus for determining photoresist pattern linearity. The method and apparatus comprises a substrate and a measuring pattern (26) printed on the substrate comprising a series of parallel lines (37) having a line width (36) and having a pre-determined pitch. By magnifying the semiconductor wafer on which the pattern feature (34) is printed and analyzing the magnified wafer from a top down view, the linearity of the pattern feature (34) can be determined from the amount of shift in the edges of the pattern feature (34). By utilizing the method and apparatus for other pattern features, the linearity of the entire pattern can be determined.

Abstract: A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (114) in a region between the trenches (113). A second semiconductor material (116) is deposited over the trenches (113) to fill the trenches (113) to a height below the first semiconductor material (112) top surface. A first insulator (130) is selectively formed over the second semiconductor material (116). The pad nitride (114) and a portion of the first semiconductor material (112) between the trenches (113) are removed to isolate element regions of the wafer (100) and form straps (142) having a low resistance.

Abstract: A nitride hard mask (230) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches (216) on a semiconductor wafer (200). The memory cell deep trenches (216) are separated from active areas (212) by a region of substrate (212). A nitride hard mask (230) is formed over the semiconductor wafer (200). The wafer (200) is patterned with the nitride hard mask (230), and the wafer (200) is etched to remove the region of substrate (212) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask (230) is used.

Abstract: A nitride hard mask (230) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches (216) on a semiconductor wafer (200). The memory cell deep trenches (216) are separated from active areas (212) by a region of substrate (212). A nitride hard mask (230) is formed over the semiconductor wafer (200). The wafer (200) is patterned with the nitride hard mask (230), and the wafer (200) is etched to remove the region of substrate (212) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask (230) is used.

Abstract: A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (114) in a region between the trenches (113). A second semiconductor material (116) is deposited over the trenches (113) to fill the trenches (113) to a height below the first semiconductor material (112) top surface. A first insulator (130) is selectively formed over the second semiconductor material (116). The pad nitride (114) and a portion of the first semiconductor material (112) between the trenches (113) are removed to isolate element regions of the wafer (100) and form straps (142) having a low resistance.

Abstract: An alternating phase shift mask (400) and method of manufacturing thereof including assist edges (450) and (452) surrounding a main phase edge (420). Assist edges (450) and (452) improve the resolution of the alternating phase shift mask (400), thus enabling the patterning of smaller size features on a semiconductor wafer.

Abstract: A method for providing contrast for alignment marks after a blanket metal deposition is disclosed. A trench is provided in a first region and a trench is provided in an alignment mark region of a semiconductor wafer. A first metal is deposited on the wafer, and the first metal is blocked from filling the trench in the alignment mark region to maintain the trench in the alignment mark region in an unfilled state. The wafer is planarized to remove the first metal from a top surface. A blanket depositing of a second metal layer is performed on the first region and the alignment mark region such that the trench in the alignment mark region is suitable for use as a scattering alignment mark.

Abstract: Method and apparatus for determining photoresist pattern linearity. The method and apparatus comprises a substrate and a measuring pattern (26) printed on the substrate comprising a series of parallel lines (37) having a line width (36) and having a pre-determined pitch. By magnifying the semiconductor wafer on which the pattern feature (34) is printed and analyzing the magnified wafer from a top down view, the linearity of the pattern feature (34) can be determined from the amount of shift in the edges of the pattern feature (34). By utilizing the method and apparatus for other pattern features, the linearity of the entire pattern can be determined.

Abstract: A semiconductor wafer structure in a overlay pattern that permits determination of overlay and critical dimension features by CD SEM in a single pass along a given axis, comprising: a) a center feature section that provides a critical dimension point along a given axis; b) plurality of smaller sections positioned adjacent to the center feature section along the given axis that include a plurality of spaces between each of the plurality of smaller sections; and c) a plurality of displacement lines adjacent to the plurality of the smaller sections to displace a plurality of spaces.