Patents by Inventor Tobias Webel
Tobias Webel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953982Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.Type: GrantFiled: July 19, 2022Date of Patent: April 9, 2024Assignee: International Business Machines CorporationInventors: Alejandro Alberto Cook Lobo, Andrew A. Turner, Christian Jacobi, Eberhard Engler, Edward C. McCain, Kevin P. Low, Phillip John Restle, Pradeep Bhadravati Parashurama, Tobias Webel, Alper Buyuktosunoglu, Karl Evan Smock Anderson, Sean Michael Carey, Kennedy Cheruiyot, Daniel Kiss, Isidore G. Bendrihem, Ian Krispin Carmichael
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Publication number: 20240095879Abstract: In one implementation, a method of generating an image is performed by a device including one or more processors and non-transitory memory. The method includes generating a first resolution function based on a formula with a set of variables having a first set of values. The method includes generating a first image based on first content and the first resolution function. The method includes detecting a resolution constraint. The method includes generating a second resolution function based on the formula with the set of variables having a second set of values, wherein the second resolution function has a summation value that satisfies the resolution constraint. The method includes generating a second image based on second content and the second resolution function.Type: ApplicationFiled: September 18, 2023Publication date: March 21, 2024Inventors: Andreas Gapel, Nitin Nandakumar, Sabine Webel, Tobias Eble
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Publication number: 20240028095Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.Type: ApplicationFiled: July 19, 2022Publication date: January 25, 2024Inventors: Tobias Webel, Alejandro Alberto Cook Lobo, Andrew A. Turner, CHRISTIAN JACOBI, Eberhard Engler, Edward C. McCain, Kevin P. Low, Phillip John Restle, Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, KARL EVAN SMOCK ANDERSON, Sean Michael Carey, KENNEDY CHERUIYOT, Daniel Kiss, Isidore G. Bendrihem, Eric Jason Fluhr, IAN KRISPIN CARMICHAEL, Gregory Scott Still
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Publication number: 20240028447Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.Type: ApplicationFiled: July 19, 2022Publication date: January 25, 2024Inventors: Alejandro Alberto Cook Lobo, Andrew A. Turner, CHRISTIAN JACOBI, Eberhard Engler, Edward C. McCain, Kevin P. Low, Phillip John Restle, Pradeep Bhadravati Parashurama, Tobias Webel, Alper Buyuktosunoglu, KARL EVAN SMOCK ANDERSON, Sean Michael Carey, KENNEDY CHERUIYOT, Daniel Kiss, Isidore G. Bendrihem, IAN KRISPIN CARMICHAEL
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Patent number: 11817697Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.Type: GrantFiled: April 5, 2022Date of Patent: November 14, 2023Assignee: International Business Machines CorporationInventors: Adam Benjamin Collura, Michael Romain, William V. Huott, Pawel Owczarczyk, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Alper Buyuktosunoglu, Tobias Webel, Michael Joseph Cadigan, Jr., Paul Jacob Logsdon, Sean Michael Carey, Stefan Payer, Karl Evan Smock Anderson, Mark Cichanowski
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Patent number: 11789518Abstract: Embodiments relate to a system, program product, and method for mitigating voltage overshoot in one or more cores in a multicore processing device including a plurality of cores. The method includes determining, in real-time, an indication of power consumption within each core of the one or more cores. The method also includes determining, through the indication of power consumption, a voltage overshoot condition in the one or more cores. The method further includes increasing, for the one or more cores, a power demand thereof. The method also includes increasing, subject to the increasing the power demand, power delivery to the one or more cores, thereby at least arresting the rate of increase of the voltage overshoot.Type: GrantFiled: June 22, 2021Date of Patent: October 17, 2023Assignee: International Business Machines CorporationInventors: Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, Ramon Bertran Monfort, Tobias Webel, Srinivas Bangalore Purushotham, Preetham M. Lobo
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Publication number: 20230318286Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.Type: ApplicationFiled: April 5, 2022Publication date: October 5, 2023Inventors: Adam Benjamin COLLURA, Michael ROMAIN, William V. HUOTT, Pawel OWCZARCZYK, Christian JACOBI, Anthony SAPORITO, Chung-Lung K. SHUM, Alper BUYUKTOSUNOGLU, Tobias WEBEL, Michael Joseph CADIGAN, JR., Paul Jacob LOGSDON, Sean Michael CAREY, Stefan PAYER, Karl Evan Smock ANDERSON, Mark CICHANOWSKI
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Patent number: 11693728Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: GrantFiled: February 11, 2022Date of Patent: July 4, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Patent number: 11586265Abstract: Embodiments relate to a system, program product, and method for proactively initiating throttle action on one or more cores in a multicore processing device to mitigate voltage droop therein. The method includes determining, in real-time, an indication of stall events within the core and determining one or more resolutions of the stall events. The method also includes determining, in real-time, a timing margin value for the core and predicting inducement of a voltage droop on the core. The method further includes integrating the resolutions of the stall events and the timing margin value for the core, determining, subject to the predicting, a throttle action for the core, and executing the throttle action on the core.Type: GrantFiled: June 16, 2021Date of Patent: February 21, 2023Assignee: International Business Machines CorporationInventors: Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, Ramon Bertran Monfort, Tobias Webel, Martin Recktenwald, Preetham M. Lobo, Srinivas Bangalore Purushotham
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Patent number: 11586267Abstract: Embodiments of the present disclosure relate to managing power provided to a semiconductor circuit to prevent undervoltage conditions. A measured voltage value describing a measured supply voltage at a first subcircuit of a semiconductor circuit can be received, the measured voltage value having a first resolution. A selected metric indicative of a supply voltage present at the first subcircuit can be received, the selected metric having a second resolution higher than the first resolution. The selected metric is calibrated to obtain a calibrated metric when a transition of the measured voltage value occurs.Type: GrantFiled: December 19, 2018Date of Patent: February 21, 2023Assignee: International Business Machines CorporationInventors: Thomas Strach, Preetham M. Lobo, Tobias Webel
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Publication number: 20220404886Abstract: Embodiments relate to a system, program product, and method for proactively initiating throttle action on one or more cores in a multicore processing device to mitigate voltage droop therein. The method includes determining, in real-time, an indication of stall events within the core and determining one or more resolutions of the stall events. The method also includes determining, in real-time, a timing margin value for the core and predicting inducement of a voltage droop on the core. The method further includes integrating the resolutions of the stall events and the timing margin value for the core, determining, subject to the predicting, a throttle action for the core, and executing the throttle action on the core.Type: ApplicationFiled: June 16, 2021Publication date: December 22, 2022Inventors: Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, Ramon Bertran Monfort, Tobias Webel, Martin Recktenwald, Preetham M. Lobo, Srinivas Bangalore Purushotham
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Publication number: 20220404890Abstract: Embodiments relate to a system, program product, and method for mitigating voltage overshoot in one or more cores in a multicore processing device including a plurality of cores. The method includes determining, in real-time, an indication of power consumption within each core of the one or more cores. The method also includes determining, through the indication of power consumption, a voltage overshoot condition in the one or more cores. The method further includes increasing, for the one or more cores, a power demand thereof. The method also includes increasing, subject to the increasing the power demand, power delivery to the one or more cores, thereby at least arresting the rate of increase of the voltage overshoot.Type: ApplicationFiled: June 22, 2021Publication date: December 22, 2022Inventors: Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, Ramon Bertran Monfort, Tobias Webel, Srinivas Bangalore Purushotham, Preetham M. Lobo
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Publication number: 20220164250Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: ApplicationFiled: February 11, 2022Publication date: May 26, 2022Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Patent number: 11275644Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: GrantFiled: December 6, 2019Date of Patent: March 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Patent number: 11150716Abstract: Various embodiments are provided for providing optimized margins of processors in a computing environment. Margins of voltage, frequency, or a combination thereof may be dynamically monitored and adjusted for a executing a processor based a workload scheduled during an event.Type: GrantFiled: February 5, 2020Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Preetham M. Lobo, Pradeep Bhadravati Parashurama, Tobias Webel, Ramon Betran Monfort, Alper Buyuktosunoglu
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Patent number: 11112846Abstract: Embodiments of the present disclosure relate to detecting undervoltage conditions at a subcircuit. A power supply current of a first subcircuit is determined over a first number of previous clock cycles. A cross current flowing between the first subcircuit and a second subcircuit is determined over the first number of previous clock cycles. An estimated momentary supply voltage present at the first subcircuit is then determined based on the power supply current of the first subcircuit over the first number of previous clock cycles and the cross current flowing between the first subcircuit and the second subcircuit over the first number of previous clock cycles.Type: GrantFiled: December 19, 2018Date of Patent: September 7, 2021Assignee: International Business Machines CorporationInventors: Thomas Strach, Preetham M. Lobo, Tobias Webel
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Publication number: 20210240247Abstract: Various embodiments are provided for providing optimized margins of processors in a computing environment. Margins of voltage, frequency, or a combination thereof may be dynamically monitored and adjusted for a executing a processor based a workload scheduled during an event.Type: ApplicationFiled: February 5, 2020Publication date: August 5, 2021Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Preetham M. LOBO, Pradeep Bhadravati PARASHURAMA, Tobias WEBEL, Ramon BETRAN MONFORT, Alper BUYUKTOSUNOGLU
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Patent number: 11029742Abstract: Embodiments are disclosed for managing voltage droop. The techniques include performing a first determination that a timing margin is less than a first threshold. The techniques also include performing a second determination that an increase in processor activity exceeds a second threshold. Additionally, the techniques include determining that a voltage droop is indicated based on the first determination and the second determination. Further, the techniques include signaling a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate.Type: GrantFiled: April 1, 2019Date of Patent: June 8, 2021Assignee: International Business Machines CorporationInventors: Tobias Webel, Preetham M Lobo, Alper Buyuktosunoglu, Ramon Bertran Monfort, Pradeep Bhadravati Parashurama, Archit Kapoor
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Patent number: 10955906Abstract: An aspect includes a plurality of throttle controllers having a modular hierarchy comprising a plurality of levels within each of a plurality of processor cores that control a plurality of throttling actions. The throttling actions include dynamic adjustment of execution suspension within the processor cores. A plurality of input throttle events at each of the processor cores is resolved based on the modular hierarchy. A chip controller coupled to the processor cores can synchronize the throttling actions between the processor cores.Type: GrantFiled: February 7, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Preetham M. Lobo, Tobias Webel, Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu
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Publication number: 20200310516Abstract: Embodiments are disclosed for managing voltage droop. The techniques include performing a first determination that a timing margin is less than a first threshold. The techniques also include performing a second determination that an increase in processor activity exceeds a second threshold. Additionally, the techniques include determining that a voltage droop is indicated based on the first determination and the second determination. Further, the techniques include signaling a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate.Type: ApplicationFiled: April 1, 2019Publication date: October 1, 2020Inventors: Tobias Webel, Preetham M. Lobo, Alper Buyuktosunoglu, Ramon Bertran Monfort, Pradeep Bhadravati Parashurama, Archit Kapoor