Patents by Inventor Tobias Webel
Tobias Webel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200257349Abstract: An aspect includes a plurality of throttle controllers having a modular hierarchy comprising a plurality of levels within each of a plurality of processor cores that control a plurality of throttling actions. The throttling actions include dynamic adjustment of execution suspension within the processor cores. A plurality of input throttle events at each of the processor cores is resolved based on the modular hierarchy. A chip controller coupled to the processor cores can synchronize the throttling actions between the processor cores.Type: ApplicationFiled: February 7, 2019Publication date: August 13, 2020Inventors: Preetham M. Lobo, Tobias Webel, Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu
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Patent number: 10725517Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.Type: GrantFiled: October 8, 2019Date of Patent: July 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
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Publication number: 20200201407Abstract: Embodiments of the present disclosure relate to detecting undervoltage conditions at a subcircuit. A power supply current of a first subcircuit is determined over a first number of previous clock cycles. A cross current flowing between the first subcircuit and a second subcircuit is determined over the first number of previous clock cycles. An estimated momentary supply voltage present at the first subcircuit is then determined based on the power supply current of the first subcircuit over the first number of previous clock cycles and the cross current flowing between the first subcircuit and the second subcircuit over the first number of previous clock cycles.Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Inventors: Thomas Strach, Preetham M. Lobo, Tobias Webel
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Publication number: 20200201413Abstract: Embodiments of the present disclosure relate to managing power provided to a semiconductor circuit to prevent undervoltage conditions. A measured voltage value describing a measured supply voltage at a first subcircuit of a semiconductor circuit can be received, the measured voltage value having a first resolution. A selected metric indicative of a supply voltage present at the first subcircuit can be received, the selected metric having a second resolution higher than the first resolution. The selected metric is calibrated to obtain a calibrated metric when a transition of the measured voltage value occurs.Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Inventors: Thomas Strach, Preetham M. Lobo, Tobias Webel
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Publication number: 20200110656Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: ApplicationFiled: December 6, 2019Publication date: April 9, 2020Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Patent number: 10598526Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.Type: GrantFiled: March 8, 2016Date of Patent: March 24, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
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Patent number: 10552250Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: GrantFiled: October 10, 2017Date of Patent: February 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Publication number: 20200033927Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.Type: ApplicationFiled: October 8, 2019Publication date: January 30, 2020Inventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
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Patent number: 10481662Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.Type: GrantFiled: November 21, 2016Date of Patent: November 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
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Patent number: 10365132Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.Type: GrantFiled: June 25, 2018Date of Patent: July 30, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
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Publication number: 20190108087Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: ApplicationFiled: October 10, 2017Publication date: April 11, 2019Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Publication number: 20180306610Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.Type: ApplicationFiled: June 25, 2018Publication date: October 25, 2018Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
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Patent number: 10048734Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.Type: GrantFiled: December 5, 2017Date of Patent: August 14, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles R. Lefurgy, Preetham M. Lobo, Richard F. Rizzolo, Malcolm S. Allen-Ware, Tobias Webel
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Publication number: 20180088650Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.Type: ApplicationFiled: November 21, 2016Publication date: March 29, 2018Inventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
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Publication number: 20180081413Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.Type: ApplicationFiled: December 5, 2017Publication date: March 22, 2018Inventors: Charles R. Lefurgy, Preetham M. Lobo, Richard F. Rizzolo, Malcolm S. Allen-Ware, Tobias Webel
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Patent number: 9874917Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.Type: GrantFiled: January 4, 2016Date of Patent: January 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles R. Lefurgy, Preetham M. Lobo, Richard F. Rizzolo, Malcolm S. Allen-Ware, Tobias Webel
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Patent number: 9811150Abstract: A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number may reduce voltage droops due to several processor cores leaving the idle state at the same time.Type: GrantFiled: November 10, 2015Date of Patent: November 7, 2017Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Alan James Drake, Michael Stephen Floyd, Charles Robert Lefurgy, Karthick Rajamani, Tobias Webel
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Publication number: 20170261354Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.Type: ApplicationFiled: March 8, 2016Publication date: September 14, 2017Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerald M. Salem, Tobias Webel
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Publication number: 20170192477Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.Type: ApplicationFiled: January 4, 2016Publication date: July 6, 2017Inventors: Charles R. Lefurgy, Preetham M. Lobo, Richard F. Rizzolo, Malcolm S. Allen-Ware, Tobias Webel
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Patent number: 9575529Abstract: A processor is provided having a common supply rail, and one or more processor cores, where the one or more processor cores share the common supply rail. Each processor core(s) includes a core dIPC value output and a core throttling signal input, and a chip power management logic, which has at least one input for inputting the core dIPC value, a threshold register for a dIPC threshold value, a chip dIPC register for a current global dIPC value, at least one chip dIPC history register for a historic global dIPC value, a subtractor providing an absolute difference of an average historic global dIPC derived from the historic global dIPC value and the current global dIPC value, a magnitude comparator providing a throttling signal when the absolute difference is above the dIPC threshold value, and at least one output for outputting a core throttling signal to the processor core(s).Type: GrantFiled: September 24, 2015Date of Patent: February 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian W. Curran, Preetham M. Lobo, Richard F. Rizzolo, James D. Warnock, Tobias Webel