Patents by Inventor Tod D. Wolf
Tod D. Wolf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8151031Abstract: A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.Type: GrantFiled: March 6, 2009Date of Patent: April 3, 2012Assignee: Texas Instruments IncorporatedInventors: Eric Biscondi, David J. Hoyle, Tod D. Wolf
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Publication number: 20100169735Abstract: Apparatus for optimizing low-density parity check (“LDPC”) decoding in a processor is disclosed herein. A processor in accordance with the present disclosure includes an LDPC decoder row update execution unit. The LDPC decoder row update execution unit accelerates an LDPC row update computation by performing a logarithm estimation and a magnitude minimization in parallel. The execution unit is activated by execution of an LDPC row update instruction. The execution unit adds a minimum of magnitudes of two input values to a difference of estimated logarithms of exponential functions of a sum and a difference of the two input values to produce a row update value.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Eric BISCONDI, David J. HOYLE, Tod D. WOLF
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Patent number: 7617440Abstract: This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process. This last active add-compare-select unit controls selection of T counter signals used in the decode.Type: GrantFiled: August 16, 2007Date of Patent: November 10, 2009Assignee: Texas Instruments IncorporatedInventor: Tod D. Wolf
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Publication number: 20090254718Abstract: A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.Type: ApplicationFiled: March 6, 2009Publication date: October 8, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Eric Biscondi, David J. Hoyle, Tod D. Wolf
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Patent number: 7594162Abstract: This invention modifies Viterbi decoding to improve BER. Within the state metric unit cascade block, this invention forces the unused ACS units decision bits to a 0 for the top rail and a 1 for the bottom rail. This invention modifies the final maximum state index with the selected decision bits from the unused ACS units. This invention uses the modified final maximum state index as the initial conditions for the k?1 traceback shift register. This invention also uses the final maximum state index to mask the generated pretraceback decision bits generated from the last block of ACS units.Type: GrantFiled: May 11, 2006Date of Patent: September 22, 2009Assignee: Texas Instruments IncorporatedInventor: Tod D. Wolf
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Publication number: 20090049367Abstract: This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process. This last active add-compare-select unit controls selection of T counter signals used in the decode.Type: ApplicationFiled: August 16, 2007Publication date: February 19, 2009Inventor: Tod D. Wolf
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Patent number: 7020827Abstract: MAP decoder with cascade architecture. Iterative Turbo decoders can use two such cascade MAP decoders with feedback in conjunction with interleaver and deinterleaver where the MAP decoders generate extrinsic information for iterations. The cascade architecture limits the required number of max* blocks which compute the logarithm of a sum of exponentials as part of the BCJR method.Type: GrantFiled: December 28, 2001Date of Patent: March 28, 2006Assignee: Texas Instruments IncorporatedInventors: Alan Gatherer, Tod D. Wolf
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Patent number: 6996765Abstract: This invention describes implementation approaches for sliding window turbo decoders. Sliding windows are used for both the beta and alpha state metric calculations. Initialization of the beta/alpha prolog sections with data from a previous iteration is employed in conjunction with a reduced length prolog section. For subsequent sliding windows the trellis values of the prolog sections are dynamically initialized based upon data derived from the signal to noise ratio of the calculated extrinsic data or the difference between the two most probable trellis states.Type: GrantFiled: September 27, 2002Date of Patent: February 7, 2006Assignee: Texas Instruments IncorporatedInventors: Tod D. Wolf, Antonio F. Mondragon-Torres, Alan Gatherer
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Patent number: 6993704Abstract: The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an interleaved forward-reverse addressing which greatly relieves the amount of memory required. This approach is in marked contrast to conventional turbo decoders which employ either a dual port main memory or a single port main memory in conjunction with a complex ping-ponged scratch memory. In the system of this invention, during each cycle accomplishes one read and one write operation in the scratch memories. If a particular location in memory, has been read, then that location is free. The next write cycle can use that location to store its data. Similarly a simplified beta RAM is implemented using a unique addressing scheme which also obviates the need for a complex ping-ponged beta RAM.Type: GrantFiled: May 8, 2002Date of Patent: January 31, 2006Assignee: Texas Instruments IncorporatedInventor: Tod D. Wolf
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Patent number: 6980605Abstract: A turbo decoder in which a sliding-block MAP decoder pipelines the forward-propagating and backward-propagating computations.Type: GrantFiled: January 29, 2001Date of Patent: December 27, 2005Inventors: Alan Gatherer, Tod D. Wolf, Armelle Laine
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Patent number: 6898254Abstract: A stopping criterion improvement for a turbo decoder that does not require division by a variable quantity. The stopping criterion improved upon generates a signal-to-noise ratio based on the mean and variance of soft-output estimates. The decoding process is aborted based on a comparison of the generated signal-to-noise ratio to a predetermined threshold.Type: GrantFiled: January 29, 2001Date of Patent: May 24, 2005Assignee: Texas Instruments IncorporatedInventors: Tod D. Wolf, William J. Ebel, Sr.
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Patent number: 6775801Abstract: This invention presents a unique implementation of the extrinsic block the turbo decoder that solves the problem of generation and use of precision extension and normalization in the alpha and beta metrics blocks. Both alpha metric inputs and beta metric inputs are processed via a circle boundary detector indicating the quadrant of the two's complement input and a precision extend block receiving an input and a corresponding circle boundary input. An extrinsics block includes a two's complement adder of the precision extended alpha and beta metrics inputs. The proposed solution obviates the need for normalization in the alpha and beta metric blocks.Type: GrantFiled: July 24, 2002Date of Patent: August 10, 2004Assignee: Texas Instruments IncorporatedInventors: Tod D. Wolf, Antonio F. Mondragon-Torres
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Patent number: 6754355Abstract: According to one embodiment of the present invention, a digital hearing device is disclosed. The digital hearing aid includes a microphone for receiving sound, which may include an analog signal. The analog signal is converted by a first converter into a digital signal. Filters are provided to divide the digital signal into multiple signal parts. A signal processor may be provided for each signal part, and performs signal processing on its respective signal part. An adder adds the output of the signal processors, which results in a processed digital signal. A second converter converts the processed digital signal back into an analog signal. A speaker then outputs the analog signal. According to another embodiment of the present invention, a method for enhancing sound is provided.Type: GrantFiled: December 7, 2000Date of Patent: June 22, 2004Assignee: Texas Instruments IncorporatedInventors: Trudy D. Stetzler, Pedro R. Gelabert, Tod D. Wolf
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Patent number: 6725409Abstract: The addition of a specialized instruction to perform the MAX star function provides a way to get better performance turbo decoding on a digital signal processor. A subtractor forms the difference between inputs A and B. The sign of this difference controls a multiplexer selection of the max function maximum of inputs A and B. The difference is applied to a lookup table built to handle both positive and negative inputs. The look up table output is summed with with the difference to form the MAX star result. The size of the lookup table is selected to match the required resolution.Type: GrantFiled: June 30, 2000Date of Patent: April 20, 2004Assignee: Texas Instruments IncorporatedInventor: Tod D. Wolf
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Publication number: 20030208716Abstract: The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an interleaved forward-reverse addressing which greatly relieves the amount of memory required. This approach is in marked contrast to conventional turbo decoders which employ either a dual port main memory or a single port main memory in conjunction with a complex ping-ponged scratch memory. In the system of this invention, during each cycle accomplishes one read and one write operation in the scratch memories. If a particular location in memory, has been read, then that location is free. The next write cycle can use that location to store its data. Similarly a simplified beta RAM is implemented using a unique addressing scheme which also obviates the need for a complex ping-ponged beta RAM.Type: ApplicationFiled: May 8, 2002Publication date: November 6, 2003Inventor: Tod D. Wolf
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Publication number: 20030140305Abstract: MAP decoder with cascade architecture. Iterative Turbo decoders can use two such cascade MAP decoders with feedback in conjunction with interleaver and deinterleaver where the MAP decoders generate extrinsic information for iterations.Type: ApplicationFiled: December 28, 2001Publication date: July 24, 2003Inventors: Alan Gatherer, Tod D. Wolf
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Publication number: 20030097630Abstract: This invention describes implementation approaches for sliding window turbo decoders. Sliding windows are used for both the beta and alpha state metric calculations. Initialization of the beta/alpha prolog sections with data from a previous iteration is employed in conjunction with a reduced length prolog section. For subsequent sliding windows the trellis values of the prolog sections are dynamically initialized based upon data derived from the signal to noise ratio of the calculated extrinsic data or the difference between the two most probable trellis states.Type: ApplicationFiled: September 27, 2002Publication date: May 22, 2003Inventors: Tod D. Wolf, Antonio F. Mondragon-Torres, Alan Gatherer
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Publication number: 20030093742Abstract: This invention presents a unique implementation of the extrinsic block the turbo decoder that solves the problem of generation and use of precision extension and normalization in the alpha and beta metrics blocks. The implementation achieves improved performance as compared to earlier approaches and does so without the added gate usage and latency resulting from normalization. The proposed solution obviates the need for normalization in the alpha and beta metric blocks.Type: ApplicationFiled: July 24, 2002Publication date: May 15, 2003Inventors: Tod D. Wolf, Antonio F. Mondragaon-Torres
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Patent number: 6473779Abstract: A combinatorial polynomial multiplier for Galois Field 256 arithmetic utilizes fewer components than an iterative Galois Field 256 arithmetic multiplier and operates 8 times faster. The combinatorial multiplier employs AND and XOR functions and operates in a single clock cycle. It can reduce the number of transistors required for the Galois Field 256 arithmetic multiplier for a Reed-Solomon decoder by almost 90%.Type: GrantFiled: October 3, 1996Date of Patent: October 29, 2002Assignee: Texas Instruments IncorporatedInventor: Tod D. Wolf
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Publication number: 20020071583Abstract: According to one embodiment of the present invention, a digital hearing device is disclosed. The digital hearing aid includes a microphone for receiving sound, which may include an analog signal. The analog signal is converted by a first converter into a digital signal. Filters are provided to divide the digital signal into multiple signal parts. A signal processor may be provided for each signal part, and performs signal processing on its respective signal part. An adder adds the output of the signal processors, which results in a processed digital signal. A second converter converts the processed digital signal back into an analog signal. A speaker then outputs the analog signal. According to another embodiment of the present invention, a method for enhancing sound is provided.Type: ApplicationFiled: December 7, 2000Publication date: June 13, 2002Inventors: Trudy D. Stetzler, Pedro R. Gelabert, Tod D. Wolf