Abstract: A downforce controller for an agricultural implement having a double-acting hydraulic cylinder. The cylinder is configured to be coupled to an agricultural row unit and an agricultural toolbar for transmitting a net downforce between the agricultural toolbar and the agricultural row unit. A first pressure in a first chamber of the cylinder and a second pressure in a second chamber of the cylinder have counteracting effects on the net downforce. A manifold coupled to the cylinder is in fluid communication with the first chamber. A pressure control valve coupled to the manifold is in fluid communication with the manifold and the first chamber.

Abstract: A downforce controller for an agricultural implement having a double-acting hydraulic cylinder. The cylinder is configured to be coupled to an agricultural row unit and an agricultural toolbar for transmitting a net downforce between the agricultural toolbar and the agricultural row unit. A first pressure in the first chamber of the cylinder and a second pressure in the second chamber of the cylinder having counteracting effects on the net downforce. A manifold coupled to the cylinder is in fluid communication with the first chamber. A pressure control valve supported by the manifold is in fluid communication with the manifold and the first chamber.

Abstract: A downforce controller for an agricultural implement having a double-acting hydraulic cylinder. The cylinder is configured to be coupled to an agricultural row unit and an agricultural toolbar for transmitting a net downforce between the agricultural toolbar and the agricultural row unit. A first pressure in a first chamber of the cylinder and a second pressure in a second chamber of the cylinder have counteracting effects on the net downforce. A manifold coupled to the cylinder is in fluid communication with the first chamber. A pressure control valve coupled to the manifold is in fluid communication with the manifold and the first chamber.

Abstract: A method for use in evaluating work estimation is provided. The method includes selecting a plurality of work units associated with a time and a level of effort. Each work unit includes one or more tasks. A total estimated duration associated with each work unit is determined based on estimated durations associated with the tasks included in the work unit. An estimation trend corresponding to the level of effort is determined. The estimation trend represents a change over time in the total estimated durations associated with the level of effort. The estimation trend is provided for presentation to a user.

Abstract: Methods and systems for managing an electric grid are described. One example method includes displaying a dashboard to a user via a computing assembly. The dashboard defines at least two cells. The example method includes receiving, at an input device of the computing assembly, a selection of a first module and appending the first module to a first of the at least two cells of the dashboard. The first module is configured to display, via the display device, at least one of electric grid data and a control to configure the electric grid.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Abstract: A system and method for incorporating design behavior and external stimulus in microdevice model feedback using a shared memory is presented. The invention describe herein uses the attached memory model to provide additional heuristics to an application executing on an emulation system's device model, which results in a more detail and real-life device emulation. The attached memory model provides a storage area for a runtime software environment to store emulation data, which is subsequently provided to the device model during emulation. The emulation data may include 1) randomization stimuli to the device model, 2) additional runtime data for checking heuristics, and 3) emulation data points that are otherwise not accessible to the device model.

Abstract: Systems and methods for facilitating visual management of an agile development process are provided. A plurality of features to be completed during an Agile development process for a software product may be identified. A respective number of predetermined time units to be allocated for development of each feature may be determined. Based at least in part upon the determination of predetermined time units, each of the features may be assigned to a respective development team included in a plurality of development teams. An illustration of the plurality of features assigned to the plurality of development teams may be generated. The illustration may include, for each feature, a respective identifier of the feature and a respective indication of the predetermined time units allocated to the feature. The generated illustration may be output for display to a user.

Abstract: A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.

Abstract: A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for: storing test patterns, a description of integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: A system and method for modifying a simulation model and optimizing an application program to produce valid hardware-identified operating conditions that are matched with simulator-identified operating conditions in order to modify a simulator accordingly is presented. A critical path coverage analyzer includes critical path measurement logic into a simulation model that injects errors into the critical path and provides visibility into the number of times that an application program exercises the critical path. The critical path coverage analyzer uses the critical path measurement logic to optimize an application program to adequately exercise and test the critical paths. Once optimized, the critical path coverage analyzer runs the optimized application program on a hardware device to produce hardware-identified operating conditions. The hardware-identified operating conditions are matched against simulator-identified operating conditions.

Abstract: First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: The input for a test generator is a plurality of test templates, each of which typically aims at covering a specific verification task. Test templates direct the production of distinct transactions, which are the atomic functional building blocks of the design-under-verification. Test templates directed to different hardware functions of the scenario are dynamically interleaved. In this way several transactions are combined together in complex statements in order to achieve a complex test scenario. The transactions are submitted to the test generator, which generates test cases, in which the different hardware functions of the scenario are exercised in combinations. Variation among the test cases is achieved through a large number of random decisions made during the generation process.

Abstract: A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Abstract: A system and method for modifying a simulation model and optimizing an application program to produce valid hardware-identified operating conditions that are matched with simulator-identified operating conditions in order to modify a simulator accordingly is presented. A critical path coverage analyzer includes critical path measurement logic into a simulation model that injects errors into the critical path and provides visibility into the number of times that an application program exercises the critical path. The critical path coverage analyzer uses the critical path measurement logic to optimize an application program to adequately exercise and test the critical paths. Once optimized, the critical path coverage analyzer runs the optimized application program on a hardware device to produce hardware-identified operating conditions. The hardware-identified operating conditions are matched against simulator-identified operating conditions.

Abstract: A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.