Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: A system and method for incorporating design behavior and external stimulus in microdevice model feedback using a shared memory is presented. The invention describe herein uses the attached memory model to provide additional heuristics to an application executing on an emulation system's device model, which results in a more detail and real-life device emulation. The attached memory model provides a storage area for a runtime software environment to store emulation data, which is subsequently provided to the device model during emulation. The emulation data may include 1) randomization stimuli to the device model, 2) additional runtime data for checking heuristics, and 3) emulation data points that are otherwise not accessible to the device model.

Abstract: A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource.

Abstract: First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: A computer implemented method, apparatus, and computer usable program code for generating statistics for a set of components in a computer chip. An exemplary computer implemented method includes identifying the set of components in the computer chip. The set of components include those components which are not clock gated. The exemplary method also includes generating statistics for the set of components. The statistics are related to clock gating testing to identify whether one or more components of the set of components can be clock gated.

Abstract: A filter internal flaw test apparatus includes a frame with a filter support and at least one pair of transducer supports. A filter is positioned in the test apparatus, and an ultrasound through transmission test and at least one ultrasound pulse echo test are performed on the filter. Data reliability is increased by positioning the pair of transducers in alignment with one another and pushing them toward one another using a force generator with a predetermined uniform force, such as via a regulated pneumatic actuator. A signal generating/receiving device is in communication with the transducers and provides the ability for analyzing the test results to determine whether the filter has an internal flaw, such as a crack or void that would render it unsatisfactory for use as a particulate filter.

Abstract: A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: Hardware logic for generating breakpoint signals (basic events) based on state changes in observed (“tagged”) hardware resource of a design under test is automatically generated and added to the simulation model of the design under test. A switch/network is included in the model for mapping basic events to complex breakpoint logic. Complex breakpoints combine basic events to form more complex breakpoints that can be selectively enabled/disabled by the simulation user. In one embodiment, user settable values are compared with complex breakpoint values to further define a complex breakpoint.

Abstract: Hardware logic for generating breakpoint signals based on state changes in observed (“tagged”) hardware resource of a design under test is automatically generated and added to the simulation model of the design under test. These breakpoints halt simulation when a user programmable event, such as an assertion, test-case failure, or trigger occurs. Allowing the end-user to define the register values used in comparison to or timing of tagged resources, results in breakpoints that can be created, changed, enabled, or disabled without rebuilding the simulation model. Because the breakpoint logic is in-circuit, it takes full advantage of the acceleration made possible by hardware simulators, while providing an interactive environment for both functional hardware verification and software development on the simulated hardware mode.

Abstract: The input for a test generator is a plurality of test templates, each of which typically aims at covering a specific verification task. Test templates direct the production of distinct transactions, which are the atomic functional building blocks of the design-under-verification. Test templates directed to different hardware functions of the scenario are dynamically interleaved. In this way several transactions are combined together in complex statements in order to achieve a complex test scenario. The transactions are submitted to the test generator, which generates test cases, in which the different hardware functions of the scenario are exercised in combinations. Variation among the test cases is achieved through a large number of random decisions made during the generation process.

Abstract: A patellar cutting guide is particularly useful in a method of minimally invasive knee arthroplasty in which an incision is made along the medial or lateral aspect of a patient's knee, exposing the knee joint. The patellar cutting guide includes a clamp configured to be located exterior to the knee over the anterior portion of the patella, a stop having at least one portion configured to extend through an incision to a location posterior to the patella, and a cutting guide defining a cutting slot. The clamp may have outwardly extending spikes for passage through the tissue overlying the patella and into engagement with the patella. The stop is movable relative to the clamp and/or cutting guide. In one embodiment, the cutting guide is offset laterally and posteriorly relative to the clamp so that the slot is aligned with a medially or laterally-formed incision in the knee.

Abstract: The car antenna ornament is a figurine for placement on a car antenna. The ornament has an elongated main body and a plurality of appendages extending from the elongated body. At least one appendage has at least one section and is rotatably connected to the main body by a joint. The ornament has an aperture dimensioned to receive a car antenna within it. The ornament is suspended either vertically or horizontally relative to the antenna. When the ornament is positioned on the antenna and the car is set in motion, the appendage rotates due to the force of the wind.

Abstract: An intramedullary stem that provides enhanced distal fixation and flexibility and methods for implanting the stem. Certain embodiments of the stem have primary and secondary flutes (or ridges or wedges). Other embodiments have transitional regions.

Abstract: The present invention provides a method for determining qualitatively or quantitatively the presence of toxic congeners of polychlorinated biphenyl in a test sample. The method includes the steps of: providing a known quantity of antibodies to the toxic polychlorinated biphenyl congener; providing a competitor that will bind to said antibodies in competition with the toxic polychlorinated biphenyl congener and having a lower affinity to said antibodies than said antibodies have to the toxic polychlorinated biphenyl congener; incubating said antibodies and said competitor in the presence of a test sample; and detecting the presence of the toxic polychlorinated biphenyl toxic congener in the test sample.

Abstract: A method for determining qualitatively or quantitatively the presence of polychlorinated biphenyl in a test sample. The method includes the steps of: providing a known quantity of antibodies to polychlorinated biphenyl; providing a competitor that will bind to said antibodies in competition with polychlorinated biphenyl and having a lower affinity to said antibodies than said antibodies have to polychlorinated biphenyl; incubating said antibodies and said competitor in the presence of a test sample; and detecting the presence of polychlorinated biphenyl in the test sample. The competitor used in this method has one of the following structures: ##STR1## wherein A is selected from the group consisting of --NH--, --S--, --O--, --CH.sub.2 --, --NH--C(O)--, --C(O)--NH--, --NH--C(O)--NH--, --NH--C(S)--NH--, --N(CH.sub.3)--, --N(CH.sub.3).sub.2 --, and --O--C(S)--NH--; B is preferably a single bond or an organic or inorganic group; C is selected from the group consisting of --CO.sub.2 H, --NH.sub.