Patents by Inventor Todd Abbott
Todd Abbott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8614473Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.Type: GrantFiled: July 18, 2011Date of Patent: December 24, 2013Assignee: Micron Technology, Inc.Inventor: Todd Abbott
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Publication number: 20130297391Abstract: Embodiments of the invention are directed to systems, methods and computer program products for implementing rule-based offer association, queuing input information for performing rule-based offer association, and implementing an intelligent offer tool for determining whether to present an offer to a user. The invention enables an entity to send targeted offers to a user that enables the user to receive at least one of a discount or a rebate on a purchase from a merchant.Type: ApplicationFiled: June 21, 2012Publication date: November 7, 2013Applicant: Bank of America CorporationInventors: Matthew Brian Cincera, Tushar Shah, Srinath Nagarajan, Robert L. Abbott, Matthew Laine Donlan, Michael Bassett, Todd Abbott
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Publication number: 20130297392Abstract: Embodiments of the invention are directed to systems, methods and computer program products for implementing rule-based offer association, queuing input information for performing rule-based offer association, and implementing an intelligent offer tool for determining whether to present an offer to a user. The invention enables an entity to send targeted offers to a user that enables the user to receive at least one of a discount or a rebate on a purchase from a merchant.Type: ApplicationFiled: June 21, 2012Publication date: November 7, 2013Applicant: Bank of America CorporationInventors: Matthew Brian Cincera, Tushar Shah, Srinath Nagarajan, Robert Abbott, Matthew Laine Donlan, Michael Bassett, Todd Abbott
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Patent number: 8482050Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.Type: GrantFiled: July 18, 2011Date of Patent: July 9, 2013Assignee: Micron Technology, Inc.Inventor: Todd Abbott
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Publication number: 20110316068Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.Type: ApplicationFiled: July 18, 2011Publication date: December 29, 2011Applicant: Micron Technology, Inc.Inventor: Todd Abbott
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Patent number: 7982255Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.Type: GrantFiled: March 10, 2008Date of Patent: July 19, 2011Assignee: Micron Technology, Inc.Inventor: Todd Abbott
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Publication number: 20110159698Abstract: A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.Type: ApplicationFiled: August 24, 2006Publication date: June 30, 2011Applicant: Micron Technology, Inc.Inventors: Kevin Torek, Todd Abbott, Sandra Tagg, Amy Weatherly
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Patent number: 7723185Abstract: A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate incorporating the flash cell.Type: GrantFiled: March 10, 2008Date of Patent: May 25, 2010Assignee: Micron Technology, Inc.Inventor: Todd Abbott
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Publication number: 20080149994Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.Type: ApplicationFiled: March 10, 2008Publication date: June 26, 2008Inventor: Todd Abbott
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Publication number: 20080153233Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.Type: ApplicationFiled: March 10, 2008Publication date: June 26, 2008Inventor: Todd Abbott
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Patent number: 7342272Abstract: A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate incorporating the flash cell.Type: GrantFiled: August 31, 2005Date of Patent: March 11, 2008Assignee: Micron Technology, Inc.Inventor: Todd Abbott
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Publication number: 20070090363Abstract: DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.Type: ApplicationFiled: July 25, 2005Publication date: April 26, 2007Inventor: Todd Abbott
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Publication number: 20070063262Abstract: A NAND memory array has a plurality of rows of memory cells and a plurality of columns of NAND strings of memory cells. Each NAND string is selectively connected to a bit line through a drain select gate of the respective column. Each of the drain select gates has a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer. Each of the memory cells of each of the NAND strings has a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer. The first dielectric layer is thicker than the second dielectric layer.Type: ApplicationFiled: November 17, 2006Publication date: March 22, 2007Inventors: Michael Violette, Garo Derderian, Todd Abbott
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Publication number: 20070048935Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.Type: ApplicationFiled: August 31, 2005Publication date: March 1, 2007Inventor: Todd Abbott
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Publication number: 20070018223Abstract: DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.Type: ApplicationFiled: July 31, 2006Publication date: January 25, 2007Applicant: Micron Technology Inc.Inventor: Todd Abbott
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Publication number: 20060281302Abstract: A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and semiconductor devices embodying the cells are also provided. In accordance with one embodiment of the present invention, a memory device cell layout is provided comprising four active areas positioned between selected ones of the gates and local interconnects associated with different damascene trenches of the device.Type: ApplicationFiled: July 24, 2006Publication date: December 14, 2006Applicant: Micron Technology, Inc.Inventor: Todd Abbott
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Publication number: 20060258093Abstract: A NAND memory array has a first dielectric layer formed on a first portion of a semiconductor substrate and a second dielectric layer formed on a second portion of the semiconductor substrate and adjoining the first dielectric layer. The first dielectric layer is thicker than the second dielectric layer. A first gate stack is formed on the first dielectric layer to form a drain select gate. A string of second gate stacks is formed on the second dielectric layer to form a NAND string of floating-gate memory cells. A first end of the NAND string is coupled in series with the drain select gate. A third gate stack is formed on the second dielectric layer to form a source select gate. A second end of the NAND string is coupled in series with the source select gate.Type: ApplicationFiled: July 14, 2006Publication date: November 16, 2006Inventors: Michael Violette, Garo Derderian, Todd Abbott
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Publication number: 20060134898Abstract: A method is provided for forming damascene gates and local interconnects a single process. By combining the formation of a damascene gate and local interconnect into a single process, a low cost solution is provided, having the advantages of low resistance wordlines and reduced gate length while reducing or eliminating the local interconnect to gate contact resistance. Further, the present invention provides flexible layout of active area to form small memory cells based upon the damascene gate and local interconnect structure. As such, the present invention is particularly suited for the fabrication of SRAM memory devices.Type: ApplicationFiled: February 6, 2006Publication date: June 22, 2006Inventor: Todd Abbott
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Publication number: 20060125123Abstract: DRAM cell arrays having a cell area of less than about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.Type: ApplicationFiled: January 10, 2006Publication date: June 15, 2006Inventor: Todd Abbott
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Publication number: 20060081884Abstract: The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2 DRAM devices.Type: ApplicationFiled: November 22, 2005Publication date: April 20, 2006Inventors: Todd Abbott, H. Manning