Patents by Inventor Todd Austin
Todd Austin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11748490Abstract: A computer system includes an ensemble moving target defense architecture that protects the computer system against attack using one or more composable protection layers that change each churn cycle, thereby requiring an attacker to acquire information needed for an attack (e.g., code and pointers) and successfully deploy the attack, before the layers have changed state. Each layer may deploy a respective attack information asset protection providing multiple respective attack protections each churn cycle, wherein the respective attack information asset protections may differ.Type: GrantFiled: December 30, 2021Date of Patent: September 5, 2023Assignee: REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Todd Austin, Valeria Bertacco, Mark Gallagher, Baris Kasikci
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Publication number: 20220277072Abstract: A method of securing a virtual address space against unauthorized access from an unauthorized agent includes generating a superimposed address space corresponding to the virtual address space, dilating the superimposed address space by inserting dununy memory at a plurality of locations in the superimposed address space, and displacing the superimposed address space by shifting a segment of the superimposed address space by a d-bit key. A computer processor includes a memory and a dedicated functional unit in a stage of a pipeline of the computer processor, the computer processor including an instruction that when executed by the dedicated functional unit causes the computer processor to translate one or more pointers between displaced and dilated address spaces of the memory and virtual address spaces of the memory.Type: ApplicationFiled: August 17, 2020Publication date: September 1, 2022Inventors: Todd Austin, Valeria Bertacco, Mark Gallagher, Baris Kasikci, Lauren Biernacki
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Patent number: 11392495Abstract: Systems and methods are provided for accurately simulating memory operations of a multi-compute-engine system, such as a multi-core system. Simulation speed can be increased by consolidation location and state information associated with data stored in one or more caches of a simulated cache hierarchy. This consolidation of information can be reflected in a single cache line map or flat cache. Accordingly, searches for data (and copies of the data) in each and every cache of the simulated cache hierarchy can be performed fast and with greater efficiency than conventional simulation systems that operate using sequential, cache-by-cache searching, while maintaining data coherency.Type: GrantFiled: February 8, 2019Date of Patent: July 19, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Ryan D. Menhusen, Todd Austin Carrington
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Publication number: 20220129563Abstract: A computer system includes an ensemble moving target defense architecture that protects the computer system against attack using one or more composable protection layers that change each churn cycle, thereby requiring an attacker to acquire information needed for an attack (e.g., code and pointers) and successfully deploy the attack, before the layers have changed state. Each layer may deploy a respective attack information asset protection providing multiple respective attack protections each churn cycle, wherein the respective attack information asset protections may differ.Type: ApplicationFiled: December 30, 2021Publication date: April 28, 2022Inventors: Todd Austin, Valeria Bertacco, Mark Gallagher, Baris Kasikci
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Patent number: 11232212Abstract: A computer system includes an ensemble moving target defense architecture that protects the computer system against attack using a plurality of composable protection layers that change each churn cycle, thereby requiring an attacker to acquire information needed for an attack (e.g., code and pointers) and successfully deploy the attack, before the layers have changed state. Each layer may deploy a different attack information asset protection providing multiple different attack protections each churn cycle.Type: GrantFiled: August 21, 2019Date of Patent: January 25, 2022Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Todd Austin, Valeria Bertacco, Mark Gallagher, Baris Kasikci
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Publication number: 20200387438Abstract: Systems and methods are provided for accurately simulating a hardware computing system. Application programming interfaces (APIs) are called within process code, the process being executed in simulation of the hardware computing system to start, stop, pause, and/or end tracking of one or more hardware events correlated to data about which a user wishes to receive statistics. Defining APIs within the process code allows per-process and per-instruction level granularity in the statistics.Type: ApplicationFiled: June 10, 2019Publication date: December 10, 2020Inventors: TODD AUSTIN CARRINGTON, Ryan D. Menhusen, John L. Byrne
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Patent number: 10834301Abstract: A miniature camera (1) comprising at least one SMA actuator wire (11) arranged to effect focus, zoom or optical image stabilization. The SMA actuator wire (11) is coated with an electrically insulating layer (40) of thickness in the range from 0.3 ?m to 10 ?m. The layer (40) provides electrical insulation whilst permitting cooling that provides a rapid response time of the SMA actuator wire (11).Type: GrantFiled: September 11, 2014Date of Patent: November 10, 2020Assignees: CAMBRIDGE MECHATRONICS LIMITED, HUTCHINSON TECHNOLOGY INCORPORATEDInventors: Andrew Benjamin David Brown, Peter Francis Ladwig, Richard Rodger Jenneke, Timothy Alan McDaniel, Paul Valentine Pesavento, Todd Austin Peter, Bryan John Scheele
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Publication number: 20200254582Abstract: A jig assembly is disclosed herein for holding a mower blade and a grinding tool during a sharpening operation on the mower blade. The jig assembly includes a mast, a fixture portion, and a jig portion. The fixture portion and jog portion can be mounted to the mast. The jig portion can include an arm and a tool-seat. The arm can include at least a first link and a second link movable relative to one another. The first link can be pivotally connected to the mast with a first pin defining an arm pivot axis. The first link and the second link can be interconnected whereby the second link is prevented from rotating in any plane that contains the arm pivot axis. The tool-seat can be disposed on the second link.Type: ApplicationFiled: March 2, 2018Publication date: August 13, 2020Inventor: TODD AUSTIN
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Publication number: 20200257622Abstract: Systems and methods are provided for accurately simulating memory operations of a multi-compute-engine system, such as a multi-core system. Simulation speed can be increased by consolidation location and state information associated with data stored in one or more caches of a simulated cache hierarchy. This consolidation of information can be reflected in a single cache line map or flat cache. Accordingly, searches for data (and copies of the data) in each and every cache of the simulated cache hierarchy can be performed fast and with greater efficiency than conventional simulation systems that operate using sequential, cache-by-cache searching, while maintaining data coherency.Type: ApplicationFiled: February 8, 2019Publication date: August 13, 2020Inventors: RYAN D. MENHUSEN, TODD AUSTIN CARRINGTON
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Publication number: 20200110884Abstract: A computer system includes an ensemble moving target defense architecture that protects the computer system against attack using a plurality of composable protection layers that change each churn cycle, thereby requiring an attacker to acquire information needed for an attack (e.g., code and pointers) and successfully deploy the attack, before the layers have changed state. Each layer may deploy a different attack information asset protection providing multiple different attack protections each churn cycle.Type: ApplicationFiled: August 21, 2019Publication date: April 9, 2020Inventors: Todd Austin, Valeria Bertacco, Mark Gallagher
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Publication number: 20170075192Abstract: Insulation of components of an SMA actuation arrangement in a miniature camera A miniature camera comprises an SMA actuator arrangement including at least one SMA actuator wire arranged to effect focus, zoom or optical image stabilization. At least one component of the SMA actuator arrangement that is not the SMA actuator wire is coated with an electrically insulating layer, thereby reducing the risk of short circuiting of the drive current of the SMA actuator wire. The SMA actuator wire may not be coated at all.Type: ApplicationFiled: March 2, 2015Publication date: March 16, 2017Applicants: CAMBRIDGE MECHATRONICS LIMITED, HUTCHINSON TECHNOLOGY INCORPORATEDInventors: Benjamin BROWN, Peter Francis LADWIG, Paul Valentine PESAVENTO, Todd Austin PETER
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Publication number: 20160227088Abstract: A miniature camera (1) comprising at least one SMA actuator wire (11) arranged to effect focus, zoom or optical image stabilization. The SMA actuator wire (11) is coated with an electrically insulating layer (40) of thickness in the range from 0.3 ?m to 10 ?m. The layer (40) provides electrical insulation whilst permitting cooling that provides a rapid response time of the SMA atuator wire (11).Type: ApplicationFiled: September 11, 2014Publication date: August 4, 2016Applicants: CAMBRIDGE MECHATRONICS LIMITED, HUTCHINSON TECHNOLOGY INCORPORATEDInventors: Andrew Benjamin David BROWN, Peter Francis LADWIG, Richard Rodger JENNEKE, Timothy Alan MCDANIEL, Paul Valentine PESAVENTO, Todd Austin PETER, Bryan John SCHEELE
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Publication number: 20120262484Abstract: Embodiments of the present invention are generally directed to devices, methods and instructions encoded on computer readable media for capturing motion and analyzing the captured motion at a portable computing device. In one exemplary embodiment, a motion capture and analysis application is provided. The application, when executed on a portable computing device, is configured to capture video of a subject (i.e., person) while the subject performs a selected action. The motion capture and analysis application provides various tools that allow an application user (e.g., trainer) to evaluate the motion of the subject during performance of the action.Type: ApplicationFiled: March 14, 2012Publication date: October 18, 2012Applicant: KINESIOCAPTURE, LLCInventors: David William Gottfeld, Robert Douglas Harris, Todd Austin Wright
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Patent number: 7598766Abstract: A fabrication technique called “component and polymorphic network,” in which semiconductor chips are made from small prefabricated bare electronic component dies, e.g., application specific integrated circuits (ASICs), that are assembled according to designer specifications, and bonded to a semiconductor substrate comprising the polymorphic network. The component and polymorphic network assembly has a low overhead for producing custom chips. In another exemplary embodiment, the polymorphic network can be combined with functional components in a single die. The interconnect scheme for ports on the polymorphic network can be configured or reconfigured with configuration data prior to the runtime of an application, to achieve different interconnect schemes.Type: GrantFiled: January 9, 2008Date of Patent: October 6, 2009Assignees: University of Washington, Microsoft Corporation, Regents of the U of MichiganInventors: Martha Mercaldi-Kim, Mark Oskin, John Davis, Todd Austin, Mojtaba Mehrara
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Patent number: 7475394Abstract: A method for analyzing the performance of a program when running in an interpreted environment. An interpreter is a program that translates and executes another program. To analyze a binary in an interpreted environment, a mechanism is used to indicate points in the program at source, intermediate, or binary showing where information about the system is to be tracked/profiled/analyzed. Once these analysis points are determined, triggers are created in a separate file or inserted via program instrumentation into the binary to indicate to the interpreter when the analysis triggers need to be processed. The system being analyzed is then run via an interpreter. When one of these triggers occurs during execution, the interpreter calls analysis code passing it the appropriate information so that it may track statistics, metrics, and information about the program corresponding to the trigger.Type: GrantFiled: December 5, 2003Date of Patent: January 6, 2009Assignee: ARM LimitedInventors: Brad Calder, Todd Austin, Don Yang, Timothy Sherwood
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Publication number: 20080164907Abstract: A fabrication technique called “component and polymorphic network,” in which semiconductor chips are made from small prefabricated bare electronic component dies, e.g., application specific integrated circuits (ASICs), that are assembled according to designer specifications, and bonded to a semiconductor substrate comprising the polymorphic network. The component and polymorphic network assembly has a low overhead for producing custom chips. In another exemplary embodiment, the polymorphic network can be combined with functional components in a single die. The interconnect scheme for ports on the polymorphic network can be configured or reconfigured with configuration data prior to the runtime of an application, to achieve different interconnect schemes.Type: ApplicationFiled: January 9, 2008Publication date: July 10, 2008Applicant: University of WashingtonInventors: Martha Mercaldi-Kim, Mark Oskin, John Davis, Todd Austin, Mojtaba Mehrara
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Publication number: 20070288798Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock.Type: ApplicationFiled: August 16, 2007Publication date: December 13, 2007Applicants: ARM Limited, University of MichiganInventors: Krisztian Flautner, Todd Austin, David Blaauw, Trevor Mudge
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Publication number: 20060200699Abstract: An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially without error. When operating outside of this typical-case range but inside the specified range of permitted values for the run-time variable operating parameters, then the error detection and error repair circuit 6 operate to repair the errors which occur.Type: ApplicationFiled: December 13, 2005Publication date: September 7, 2006Applicants: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, David Bull, Todd Austin, David Blaauw, Trevor Mudge
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Publication number: 20060018171Abstract: There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.Type: ApplicationFiled: June 13, 2005Publication date: January 26, 2006Applicant: ARM LimitedInventors: Todd Austin, David Blaauw, Trevor Mudge, Dennis Sylvester, Krisztian Flautner
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Publication number: 20050207521Abstract: A data processing apparatus and method are provided for recovering from errors in the data processing apparatus. The data processing apparatus comprises processing logic operable to perform a data processing operation, and a plurality of sampling circuits, each sampling circuit being located at a predetermined point in the processing logic and operable to sample a value of an associated digital signal generated by the processing logic at that predetermined point. Each of the sampling circuits includes a backup latch for storing a backup copy of the associated digital signal value, and at least one of the sampling circuits is operable to temporally sample the value of the associated digital signal at a first time and at at least one later time, and to store as a backup copy a selected one of the sampled values representing a correct value.Type: ApplicationFiled: February 4, 2005Publication date: September 22, 2005Applicants: ARM Limited, University of MichiganInventors: Seokwoo Lee, Todd Austin