Patents by Inventor Todd E. Humes

Todd E. Humes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11403505
    Abstract: An RFID integrated circuit, in addition to having conductive pads to electrically couple to an antenna, may also include a conductive bridge configured to electrically connect different portions of the antenna together. In some embodiments, the conductive bridge may be used to form a multi-turn antenna segment.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: August 2, 2022
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Todd E. Humes, Ronald A. Oliver
  • Patent number: 10936929
    Abstract: An RFID integrated circuit, in addition to having conductive pads to electrically couple to an antenna, may also include a conductive bridge configured to electrically connect different portions of the antenna together. In some embodiments, the conductive bridge may be used to form a multi-turn antenna segment.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: March 2, 2021
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Todd E. Humes, Ronald A. Oliver
  • Patent number: 10733395
    Abstract: Embodiments are directed to restricting access to Radio Frequency Identification (RFID) tag information based on location. Access to RFID tag information may be restricted at the reader level, at the requester level, and at the network level. When reader-level restrictions exist, devices may be prevented from inventorying tags and retrieving information from tags. When requester-level restrictions exist, a requester or device may be prevented from receiving tag information from inventoried tags or a network. When network-level restrictions exist, a network may discard or otherwise restrict tag information received from devices.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 4, 2020
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Scott A. Cooper, Kurt E. Sundstrom, Todd E. Humes, Alberto Pesavento
  • Patent number: 10311353
    Abstract: An RFID integrated circuit, in addition to having conductive pads to electrically couple to an antenna, may also include a conductive bridge configured to electrically connect different portions of the antenna together. In some embodiments, the conductive bridge may be used to form a multi-turn antenna segment.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: June 4, 2019
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Todd E. Humes, Ronald A. Oliver
  • Patent number: 10204245
    Abstract: Embodiments are directed to restricting access to Radio Frequency Identification (RFID) tag information based on location. Access to RFID tag information may be restricted at the reader level, at the requester level, and at the network level. When reader-level restrictions exist, devices may be prevented from inventorying tags and retrieving information from tags. When requester-level restrictions exist, a requester or device may be prevented from receiving tag information from inventoried tags or a network. When network-level restrictions exist, a network may discard or otherwise restrict tag information received from devices.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: February 12, 2019
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Scott A. Cooper, Kurt E. Sundstrom, Todd E. Humes, Alberto Pesavento
  • Patent number: 9959435
    Abstract: Embodiments are directed to restricting access to Radio Frequency Identification (RFID) tag information based on location. Access to RFID tag information may be restricted at the reader level, at the requester level, and at the network level. When reader-level restrictions exist, devices may be prevented from inventorying tags and retrieving information from tags. When requester-level restrictions exist, a requester or device may be prevented from receiving tag information from inventoried tags or a network. When network-level restrictions exist, a network may discard or otherwise restrict tag information received from devices.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 1, 2018
    Assignee: IMPINJ, INC.
    Inventors: Christopher J. Diorio, Scott A. Cooper, Kurt E. Sundstrom, Todd E. Humes, Alberto Pesavento
  • Patent number: 8759937
    Abstract: A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such as to a second conductivity type opposite that of the first conductivity type. A second well is disposed within the first well. A region of metal-containing material is disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well. In one embodiment, a second well contact is disposed in a portion of the second well.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: June 24, 2014
    Assignee: Synopsys, Inc.
    Inventors: Yanjun Ma, Ronald A. Oliver, Todd E. Humes, Jaideep Mavoori
  • Patent number: 8350665
    Abstract: RFID tags are commanded to generate a pilot tone in their backscatter. When the backscattered pilot tone is received in the reader, the pilot tone is used to estimate the tag period/frequency. Then, the estimate is used to seed and lock a symbol timing recovery loop, which provides a detected signal to one or more correlators for detecting the tag preamble. A delayed version of the received tag signal is compared against a baseline signal threshold established from the received signal to detect the pilot tone.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: January 8, 2013
    Assignee: Impinj, Inc.
    Inventors: Kurt E. Sundstrom, Scott A. Cooper, Amir Sarajedini, Aanand Esterberg, Todd E. Humes, Christopher J. Diorio
  • Patent number: 8294582
    Abstract: Apparatus and systems may include integrated circuits for use with Radio Frequency Identification (RFID) tags having an antenna structure with at least three coupling ends. The integrated circuits may include three or more nodes corresponding respectively to the at least three coupling ends, and a modulator switch to receive a single modulator switching signal input. Methods may include those used to form and operate such circuits. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: October 23, 2012
    Assignee: Impinj, Inc.
    Inventors: Todd E. Humes, Ronald A. Oliver
  • Patent number: 8224610
    Abstract: A method of calibrating an oscillator within a Radio-Frequency Identification (RFID) tag includes storing a plurality of calibration values within a memory structure. Each of the calibration values corresponds to a respective oscillation frequency of the oscillator. A selected calibration value is selected from the plurality of calibration values stored, according to a first selection criterion. The oscillator is then calibrated in accordance with the selected calibration value.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: July 17, 2012
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Vadim Gutnik, Todd E. Humes
  • Patent number: 8122307
    Abstract: One Time Programmable (OTP) memory structures and methods for pretesting the support circuitry are provided. A group of dedicated test cells associated with one or more groups of regular OTP cells are used to test the support circuitry for the regular OTP cells. The dedicated cells are programmed and read. The read values are compared to the programmed values or expected values. As a result of the comparison, failing memories may be designated “Not Usable”, while regular OTP cells of passing memories can be programmed for their purpose resulting in elimination of wasted memories during test.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: February 21, 2012
    Assignee: Synopsys, Inc.
    Inventors: Chad A. Lindhorst, Todd E. Humes, Andrew E. Horch, Ernest Allen, III
  • Patent number: 8102007
    Abstract: A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: January 24, 2012
    Assignee: Synopsys, Inc.
    Inventors: John D. Hyde, Miguel E. Figueroa, Todd E. Humes, Christopher J. Diorio, Terry D. Hass, Chad A. Lindhorst
  • Patent number: 8076707
    Abstract: A semiconductor device is provided that uses a floating gate to store analog- and digital-valued information for periods of time measured in milliseconds to hours. Charge is added to and/or removed from the floating gate by means of direct electron tunneling through the surrounding insulator, with the insulator typically being thin enough such that appreciable tunneling occurs with an insulator voltage smaller than the difference in electron affinities between the semiconductor and the insulator and/or between the floating gate and the insulator. The stored information is refreshed or updated as needed. In many applications, the stored information can be refreshed without interrupting normal circuit operation. Adding and removing charge to or from the floating gate may be performed using separate circuit inputs, to tailor the performance and response of the floating-gate device. There is no need to use a control gate in the floating-gate structures disclosed herein.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: December 13, 2011
    Assignee: Synopsys, Inc.
    Inventors: John D. Hyde, Todd E. Humes, Christopher J. Diorio, Carver A. Mead
  • Patent number: 7732887
    Abstract: A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that of the first conductivity type. A region of metal-containing material is disposed over the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well. In one embodiment, a first well contact is disposed in a portion of the first well. A second well is disposed over the substrate wherein the second well includes a material doped to the first conductivity type. In one embodiment, the first well and the second well are not in direct contact with one another.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: June 8, 2010
    Assignee: Virage Logic Corporation
    Inventors: Yanjun Ma, Ronald A. Oliver, Todd E. Humes, Jaideep Mavoori
  • Patent number: 7724571
    Abstract: Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 25, 2010
    Assignee: Virage Logic Corporation
    Inventors: Chad A. Lindhorst, Todd E. Humes, Alex May, Agustinus Sutandi
  • Patent number: 7724570
    Abstract: Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 25, 2010
    Assignee: Virage Logic Corporation
    Inventors: Chad A. Lindhorst, Todd E. Humes, Alex May, Agustinus Sutandi
  • Patent number: 7667589
    Abstract: RFID tags have an on-chip antenna and an off-chip antenna. One of the antennas can become uncoupled if the proper signal is received, while the other antenna may still operate. The uncoupled antenna can be the larger one, for example the off-chip antenna. Then the tag can then be read only by the smaller antenna, which effectively reduces the range of the RFID tag, but without disabling it entirely.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: February 23, 2010
    Assignee: Impinj, Inc.
    Inventors: Dimitri C. Desmons, Ronald A. Oliver, Christopher J. Diorio, Todd E. Humes
  • Patent number: 7616120
    Abstract: Apparatus and systems may include integrated circuits for use with Radio Frequency Identification (RFID) tags having an antenna structure with at least three coupling ends. The integrated circuits may include three or more nodes corresponding respectively to the at least three coupling ends, and a modulator switch to receive a single modulator switching signal input. Methods may include those used to form and operate such circuits. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: November 10, 2009
    Assignee: Impinj, Inc.
    Inventors: Todd E. Humes, Ronald A. Oliver
  • Patent number: 7548460
    Abstract: Hot-electron injection driven by hole impact ionization in the channel-to-drain junction of a p-channel MOSFET provides a new mechanism for writing a floating-gate memory. Various pFET floating-gate structures use a combination of this mechanism and electron tunneling to implement nonvolatile analog memory, nonvolatile digital memory, or on-line learning in silicon. The memory is nonvolatile because the devices use electrically isolated floating gates to store electronic charge. The devices enable on-line learning because the electron injection and tunneling mechanisms that write the memory can occur during normal device operation. The memory updates and learning are bidirectional because the injection and tunneling mechanisms add and remove electrons from the floating gate, respectively. Because the memory updates depend on both the stored memory and the pFETs terminal voltages, and because they are bidirectional, the devices can implement on-line learning functions.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: June 16, 2009
    Assignee: California Institute of Technology
    Inventors: Christopher J. Diorio, Todd E. Humes
  • Patent number: 7528728
    Abstract: A circuit for an RFID tag has at least two RF ports for driving points of the antenna that may correspond to different RF polarizations. The RF ports may be driven by a common modulating signal, or by separate modulating signals. Further, the ports may be coupled and uncoupled together, responsive to a control signal. The control signal may be the same as one or both of the modulating signals.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: May 5, 2009
    Assignee: IMPINJ Inc.
    Inventors: Ronald A. Oliver, Christopher J. Diorio, Todd E. Humes