Abstract: A circuit board including: a first board material layer having a first planar surface and a first sidewall surface perpendicular to the first planar surface; a first conductive layer on the first planar surface; a second board material layer stacked on the first board material layer and having a second planar surface and a second sidewall surface perpendicular to the second planar surface; a second conductive layer on the second planar surface; and a plating on the first sidewall surface and the second sidewall surface and electrically connecting the first conductive layer and the second conductive layer.

Abstract: A package structure is disclosed. The package structure includes processor die connected to a top surface of a package substrate. The package structure further includes a DC-DC power converter attached to a bottom surface of the package substrate. The DC-DC power converter is located at least within an open area of an interconnect component that connects the bottom surface of the package substrate and a top surface of a motherboard.

Abstract: A power converter with co-packaged secondary field effect transistors (FETs) are described. The power converter can include a first circuit, a transformer connected to an output of the first circuit, and a second circuit connected to an output of the transformer. The second circuit can include an inductor, a first FET coupled between the transformer and the inductor, and a second FET coupled between the first FET and ground. The first FET and the second FET can be co-packaged as a single package.

Abstract: A server drawer comprising a plurality of Printed Circuit Boards (PCBs) respectively containing heat-generating electronic devices. The server drawer further comprises a plurality of fans configured to convectively dissipate heat from the heat-generating electronic devices. The server drawer further comprises internal partitions isolating airflow between respective PCBs of the plurality of PCBs.

Abstract: An apparatus comprising chips mounted to a substrate, wherein one or more of the chips comprises a first height and one or more of the chips comprises a second height, wherein the first height is taller than the second height. A cold plate located above the plurality of chips, wherein the cold plate includes a bottom wall and a top wall, wherein the cold plate includes a plurality of cooling fins that are attached to the bottom wall of the cold plate, wherein the cold plate accommodates the plurality of chips, wherein the chips includes chips having the first height and the second height.

Abstract: A structure is provided for a structure for providing electrical connections across a connection interface is provided. The structure may include one or more signal connections, a plurality of reference connections, and one or more high-pass filters. One or more of the reference connections is configured to connect a first reference voltage in a first region on a first side of the interface with a second reference voltage in a second region on a second side of the interface. One or more of the reference connections in a first class of reference connections is coupled one or more of the reference voltages through the one or more high-pass filters, and low-bandwidth information is communicated across the one or more reference connections in the first class of reference connection.

Abstract: A passive circuit element is disclosed. The passive circuit element includes an array of conductive pads arranged on a substrate such that a gap is formed between each of the conductive pads. The passive circuit element further includes a first wire electrically connected to a first conductive pad of the array of conductive pads such that the first wire passes through a first gap formed between a second conductive pad and a third conductive pad. The passive circuit element further includes a second wire electrically connected to a fourth conductive pad of the array of conductive pads such that the second wire passes through the first gap. At least one of the second and third conductive pads has a substantially planar side facing toward the first gap.

Abstract: A server drawer comprising a plurality of Printed Circuit Boards (PCBs) respectively containing heat-generating electronic devices. The server drawer further comprises a plurality of fans configured to convectively dissipate heat from the heat-generating electronic devices. The server drawer further comprises internal partitions isolating airflow between respective PCBs of the plurality of PCBs.

Abstract: A structure is provided for a structure for providing electrical connections across a connection interface is provided. The structure may include one or more signal connections, a plurality of reference connections, and one or more high-pass filters. One or more of the reference connections is configured to connect a first reference voltage in a first region on a first side of the interface with a second reference voltage in a second region on a second side of the interface. One or more of the reference connections in a first class of reference connections is coupled one or more of the reference voltages through the one or more high-pass filters, and low-bandwidth information is communicated across the one or more reference connections in the first class of reference connection.

Abstract: An integrated circuit package provides a high bandwidth interconnect between wafers using a very high density interconnect using a silicon bridge or a multi-layer flex between wafers. In some embodiments, more than one wafer may be mounted and connected with a rigid silicon bridge onto a common substrate. This common substrate can be matched, with respect to their coefficients of thermal expansion (CTE), to the silicon wafer. The CTE matched substrate can reduce the thermal mechanical stress on the wafers and the rigid silicon bridge interconnect. In some embodiments, a thinned silicon bridge is utilized to interconnect wafers which are mounted on separate glass substrates. The thinned bridge would allow for mechanical compliance between the wafers. In some embodiments, the wafers can be mounted onto separate glass substrates and attached with a fine pitch multi-layer flex structure which provides compliance between the wafers.

Abstract: A system and method for supporting an interconnection of processor cores, each core with functional state monitors for monitoring operations of each processor core, the processor cores interconnected using a resistive network connected between two-terminal regions being embedded in the resistive network such that each terminal of a region may be connected by controllable resistors to one or both fixed rails or by controllable resistors to one or more intermediate nodes. The resistor values are configurable to provide indirect control of the voltages across each two-terminal region, allowing full dynamic control of voltages of the two-terminal regions in a range up to the full voltage between the two voltage rails, and where a management unit accesses the functional state monitors and controls the resistor values. Feedback from functional state monitors allow the operating frequency to extend down to arbitrarily low values and up to the limits imposed by the technology.

Abstract: A semiconductor package provides a low profile connection to a bottom side of the semi-conductor package. The semi-conductor package includes a computer processor die and a substrate. The computer processor die is mounted on to a top surface of the substrate. The substrate is mounted on to a printed circuit board. A voltage regulator is coupled to the printed circuit board. A top surface of the voltage regulator is coupled to a bottom surface of the substrate. The package also includes a connector device. The connector device includes a cable configured to conduct power from an upstream source, and a low-profile connector module attached to an end of the cable. The connector module is configured to interface to a bottom surface of the voltage regulator.

Abstract: A method includes attaching an integrated circuit chip module substrate to a printed circuit board (PCB). First region(s) of a bottom surface of the module include electrical contacts to the board, and second region(s) of the bottom surface of the module lack such contacts. Mechanical structures are assembled into the second regions. These structures allow lateral motion of the module relative to the board, and are sized and placed to inhibit bending of the second regions of the module towards the board under application of a vertical force on a top surface of the module. A package for an integrated circuit may be assembled using the method.

Abstract: In an apparatus for coupling integrated circuits to printed circuit boards, a backing plate with manufactured features on the top surface includes a module lid; a planar structure; a device seated in the planar structure, with the module lid in contact with the top surface of the device; and a backing plate that contains manufactured features on one side. The backing plate is in contact with the planar structure, and a plurality of fastening mechanisms couple together the lid, the device, the planar structure, and the backing plate.

Abstract: A package structure is disclosed. The package structure includes processor die connected to a top surface of a package substrate. The package structure further includes a DC-DC power converter attached to a bottom surface of the package substrate. The DC-DC power converter is located at least within an open area of an interconnect component that connects the bottom surface of the package substrate and a top surface of a motherboard.

Abstract: An apparatus comprising chips mounted to a substrate, wherein one or more of the chips comprises a first height and one or more of the chips comprises a second height, wherein the first height is taller than the second height. A cold plate located above the plurality of chips, wherein the cold plate includes a bottom wall and a top wall, wherein the cold plate includes a plurality of cooling fins that are attached to the bottom wall of the cold plate, wherein the cold plate accommodates the plurality of chips, wherein the chips includes chips having the first height and the second height.

Abstract: Embodiment of the present invention includes a magnetic structure and a magnetic structure used in a direct current (DC) to DC energy converter. The magnetic structure has an E-core and a plate, with the plate positioned in contact or in near contact with the post surfaces of the E-core. The E-core has a base, a no-winding leg, a transformer leg, and an inductor leg. The no-winding leg, the transformer leg, and the inductor leg are perpendicular and magnetically in contact with the base. The plate is a flat slab with lateral dimensions generally larger than its thickness. The plate has a plate nose that overlaps a top no-winding leg surface of the no-winding leg with a no-winding gap area to form a no-winding gap with a no-winding gap reluctance. The plate also has a plate end that overlaps a top inductor leg surface of the inductor leg with an inductor gap area to form an inductor gap with an inductor gap reluctance. In some embodiments, e.g.

Abstract: An apparatus includes a cabinet; an air-mover attached to the cabinet; a circuit board mounted in the cabinet; and an air-cooled heat sink attached in thermal contact with a heat-generating component on the circuit board. The heat sink includes a heat sink base; primary heat removal fins protruding from the heat sink base in a direction away from the circuit board; and secondary heat removal fins protruding from the heat sink base in a direction toward the circuit board. The air-mover is configured to force air between the primary heat removal fins and between the secondary heat removal fins.

Abstract: Embodiment of the present invention includes a magnetic structure and a magnetic structure used in a direct current (DC) to DC energy converter. The magnetic structure has an E-core and a plate, with the plate positioned in contact or in near contact with the post surfaces of the E-core. The E-core has a base, a no-winding leg, a transformer leg, and an inductor leg. The no-winding leg, the transformer leg, and the inductor leg are perpendicular and magnetically in contact with the base. The plate is a flat slab with lateral dimensions generally larger than its thickness. The plate has a plate nose that overlaps a top no-winding leg surface of the no-winding leg with a no-winding gap area to form a no-winding gap with a no-winding gap reluctance. The plate also has a plate end that overlaps a top inductor leg surface of the inductor leg with an inductor gap area to form an inductor gap with an inductor gap reluctance. In some embodiments, e.g.

Abstract: The structure includes a semiconductor chip connected to a substrate via one or more solder balls. The semiconductor chip includes one or more on-chip metal winding. The structure includes a first ferromagnetic core. The first ferromagnetic core is located below the semiconductor chip and above the substrate. The structure includes a second ferromagnetic core. The second ferromagnetic core is located above the semiconductor chip. The first ferromagnetic core and the second ferromagnetic core create a magnetic loop.