Abstract: The structure includes a semiconductor chip connected to a substrate via one or more solder balls. The semiconductor chip includes one or more on-chip metal winding. The structure includes a first ferromagnetic core. The first ferromagnetic core is located below the semiconductor chip and above the substrate. The structure includes a second ferromagnetic core. The second ferromagnetic core is located above the semiconductor chip. The first ferromagnetic core and the second ferromagnetic core create a magnetic loop.

Abstract: The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate. A group III nitride transistor is formed in a trench in the SOI substrate. The activation of the group III nitride transistor is controlled by a silicon-based transistor. The silicon-based transistor that includes a portion of a silicon layer of the SOI substrate. A group III nitride transistor device is adjacent to the silicon-based transistor.

Abstract: A cold plate apparatus includes a top wall and a bottom wall that enclose a plenum for fluid flow; an inlet and an outlet each formed in one of the top wall or the bottom wall; a first active area within the plenum; a second active area within the plenum; and a partition that extends between the top wall and the bottom wall within the plenum and that separates the first active area from the second active area so that a portion of fluid flowing from the inlet to the outlet through the plenum flows through either the first active area or the second active area but not through both active areas.

Abstract: An approach for reducing unwanted magnetic coupling with conductive elements by keeping the localized magnetic field in a transformer's or inductors magnetic gap far away from any conductive elements is provided. The approach includes the use of spacers to keep the localized magnetic field in a transformer's or inductor's magnetic gap far away from any conductive elements to reduce unwanted magnetic coupling with those conductive elements. The spacers can be made from materials including ferrite, conductors and non-conducting elements.

Abstract: A cold plate apparatus includes a top wall and a bottom wall that enclose a plenum for fluid flow; an inlet and an outlet each formed in one of the top wall or the bottom wall; a first active area within the plenum; a second active area within the plenum; and a partition that extends between the top wall and the bottom wall within the plenum and that separates the first active area from the second active area so that a portion of fluid flowing from the inlet to the outlet through the plenum flows through either the first active area or the second active area but not through both active areas.

Abstract: A power converter with co-packaged secondary field effect transistors (FETs) are described. The power converter can include a first circuit, a transformer connected to an output of the first circuit, and a second circuit connected to an output of the transformer. The second circuit can include an inductor, a first FET coupled between the transformer and the inductor, and a second FET coupled between the first FET and ground. The first FET and the second FET can be co-packaged as a single package.

Abstract: A method includes attaching an integrated circuit chip module substrate to a printed circuit board (PCB). First region(s) of a bottom surface of the module include electrical contacts to the board, and second region(s) of the bottom surface of the module lack such contacts. Mechanical structures are assembled into the second regions. These structures allow lateral motion of the module relative to the board, and are sized and placed to inhibit bending of the second regions of the module towards the board under application of a vertical force on a top surface of the module. A package for an integrated circuit may be assembled using the method.

Abstract: The structure includes a substrate. The structure includes a semiconductor chip connected to the substrate via on or more solder balls. The structure includes a magnetic shielding sheet located between the substrate and the semiconductor chip.

Abstract: In an apparatus for coupling integrated circuits to printed circuit boards, a backing plate with manufactured features on the top surface includes a module lid; a planar structure; a device seated in the planar structure, with the module lid in contact with the top surface of the device; and a backing plate that contains manufactured features on one side. The backing plate is in contact with the planar structure, and a plurality of fastening mechanisms couple together the lid, the device, the planar structure, and the backing plate.

Abstract: The structure includes a semiconductor chip connected to a substrate via one or more solder balls. The semiconductor chip includes one or more on-chip metal winding. The structure includes a first ferromagnetic core. The first ferromagnetic core is located below the semiconductor chip and above the substrate. The structure includes a second ferromagnetic core. The second ferromagnetic core is located above the semiconductor chip. The first ferromagnetic core and the second ferromagnetic core create a magnetic loop.

Abstract: The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate. A group III nitride transistor is formed in a trench in the SOI substrate. The activation of the group III nitride transistor is controlled by a silicon-based transistor. The silicon-based transistor that includes a portion of a silicon layer of the SOI substrate. A group III nitride transistor device is adjacent to the silicon-based transistor.

Abstract: An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

Abstract: An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

Abstract: Method for and apparatus were fans and cable placed at the ends at the same end of a computer rack drawer. The cable ends are located between the fans and the computing elements. The bulk length of each cable passes through the region where the fans are located. Air, and optionally EMI, sealing are provided by an elastic material near the fans. In this way cables could exit the same tailstock of the drawer where fans are located. The cable ends can receive good cooling, and the distance between the cable ends and computing elements of the drawer is not lengthened by the fan position.

Abstract: Method for and apparatus were fans and cable placed at the ends at the same end of a computer rack drawer. The cable ends are located between the fans and the computing elements. The bulk length of each cable passes through the region where the fans are located. Air, and optionally EMI, sealing are provided by an elastic material near the fans. In this way cables could exit the same tailstock of the drawer where fans are located. The cable ends can receive good cooling, and the distance between the cable ends and computing elements of the drawer is not lengthened by the fan position.

Abstract: An electrical connector includes an anode for conducting an electrical supply current from a source to a destination, a cathode for conducting an electrical return current from the destination to the source, and an insulator that prevents electrical conduction between the anode and the cathode. The first and second shapes are such as to provide a conformity of one to the other, with the insulator placed therebetween and having a predetermined relatively thin thickness. A predetermined low-resistance path for the supply current is provided respectively by the anode and the cathode, and a proximity of the anode to the cathode along these paths provides a predetermined low self-inductance of the connector. The anode and the cathode each comprises a plurality of sections that are disposed at one or more predetermined angles to form a rigid assembly that accommodates a geometry between the source and the destination.

Abstract: An electrical connector includes an anode for conducting an electrical supply current from a source to a destination, a cathode for conducting an electrical return current from the destination to the source, and an insulator that prevents electrical conduction between the anode and the cathode. The first and second shapes are such as to provide a conformity of one to the other, with the insulator placed therebetween and having a predetermined relatively thin thickness. A predetermined low-resistance path for the supply current is provided respectively by the anode and the cathode, and a proximity of the anode to the cathode along these paths provides a predetermined low self-inductance of the connector. The anode and the cathode each comprises a plurality of sections that are disposed at one or more predetermined angles to form a rigid assembly that accommodates a geometry between the source and the destination.

Abstract: An electrical connector includes an anode assembly for conducting an electrical supply current from a source to a destination, the anode assembly includes an anode formed into a first shape from sheet metal or other sheet-like conducting material. A cathode assembly conducts an electrical return current from the destination to the source, the cathode assembly includes a cathode formed into a second shape from sheet metal or other sheet-like conducting material. An insulator prevents electrical conduction between the anode and the cathode. The first and second shapes are such as to provide a conformity of one to the other, with the insulator therebetween having a predetermined relatively thin thickness.

Abstract: An electrical connector includes an anode assembly for conducting an electrical supply current from a source to a destination, the anode assembly includes an anode formed into a first shape from sheet metal or other sheet-like conducting material. A cathode assembly conducts an electrical return current from the destination to the source, the cathode assembly includes a cathode formed into a second shape from sheet metal or other sheet-like conducting material. An insulator prevents electrical conduction between the anode and the cathode. The first and second shapes are such as to provide a conformity of one to the other, with the insulator therebetween having a predetermined relatively thin thickness.

Abstract: A method and apparatus that provides improved loop inductance of decoupling capacitors. Vias are moved close to the pads and close to each other. Instead of placing power and ground vias on opposite sides of the capacitor, these vias are moved around to the same side of the capacitor and are placed as close to each other as manufacturing tolerances will allow. For designs using standard two-terminal surface mount capacitors, two vias per capacitor, and standard manufacturing procedures (no vias inside pads, for example), the lowest possible loop inductance of the capacitor's connections to the printed circuit board planes is provided. This results in the lowest effective capacitor series input inductance.