Abstract: A first pixel of a given field is compared with second and third vertically aligned pixels of corresponding horizontal position of an adjacent field to produce, for each first pixel, a pixel difference signal having a value of zero if the value of the first pixel is intermediate the values of the second and third pixels, the difference signal otherwise having a value equal to the absolute value of a difference between the value of the first pixel and the value of one of the second and third pixels having a value closest to that of first pixel. The pixel difference signals are accumulated over a predetermined portion of one field period of the video signal to provide a field difference signal which is analyzed by a group of five correlators for patterns characteristic of 2-2 pull-down or 3-2 pull-down film mode sources. Flags are produced for identifying film mode operation and for identifying which of the adjacent fields to use in subsequent video processing such as de-interlacing or flicker reduction.

Abstract: Adjustment and maintenance of a phase relationship between a video signal and a scan synchronizing signal to assure proper horizontal centering is provided in a horizontal deflection system. A first phase locked loop generates a first timing signal at a first frequency, synchronously with a horizontal synchronizing component in a video signal. A presettable counting circuit operates synchronously with the first timing signal for dividing a clock signal to generate a second timing signal at a second frequency. A second phase locked loop generates a scan synchronizing signal from the second timing signal. A microprocessor may supply different numbers to a register, the output of the register being coupled to the presettable counting circuit. Different numbers change the relative phase between the first and second timing signals by incremental steps.

Abstract: A binary number is generated representative of net motion during a field interval of an interlaced video signal from which a field to field difference signal is derived having a sign bit and a group of magnitude bits. The magnitude bits are compared with a first threshold to provide a first threshold indicating signal which, with the sign bit, are applied via respective bus lines to each correlator of a group of five correlators. The correlators are addressed using variable modulo addressing to detect patterns representative of 2--2 pull down and 3-2 pull down film originated frames. Logic is provided for detecting when one and only one of the five correlators indicates film detection to verify film mode operation. Error reduction is further enhanced by comparing the field difference signal with a second threshold, higher than the first, to provide a second thresold indicating signal to each correlator via a second bus.

Abstract: A video signal clamp involves evaluating the difference between the signal level and the desired clamp level during the back porch interval. A correction signal indicates whether the signal level must be increased or decreased to establish the desired clamp level. Generation of the correction signal involves a median filter algorithm. Any required increase or decrease of the signal level occurs continuously throughout each horizontal line interval.

Abstract: A video signal to be processed is applied to a non-linear processor having an adjustable gain responsive to a control signal over at least one portion of the amplitude range of the video input signal. A sampling circuit, responsive to the video signal, generates video samples related to the video signal. A control circuit, responsive to the video samples, generates the control signal in accordance with the number of samples in at least a given amplitude range thereby controlling the percentage of samples of a given range in displayed images. Plural control and sampling circuits may be included provide control for white stretch processing, black stretch processing and video mid-point processing for enhancing contrast through out the entire video signal range.

Abstract: A video source provides a temporally interpolated video signal, a spatially interpolated video signal and a motion indicating signal. A difference signal, derived from the temporally and spatially interpolated signals, is symmetrically limited as a function of the motion signal amplitude and then combined with the temporally interpolated signal to form a motion adapted video output signal having (1) reduced motion artifacts such as smearing and loss of fine detail; (2) reduced noise sensitivity; and (3) enhanced low-contrast motion rendition.

Abstract: A two stage interpolation system provides greater bandwidth for signals compressed and expanded by interpolation, for example video signals displayed in a zoom or enlarged mode. A finite impulse response filter generates from a first signal of digital samples a second signal of digital samples representing signal points between the samples of the first signal. The first signal is delayed, but otherwise substantially unmodified. The second signal and the delayed first signal are interleaved, for example by a multiplexer, to produce a third signal of digital values having a sample density twice that of the first signal. A compensated variable interpolator derives from the third signal a fourth signal of digital samples in which the frequency content of information represented by the first signal has been changed.

Abstract: A source responsive to a composite video input signal provides line and burst frequency related timing signals. A measuring circuit responsive to the timing signals provides measurement values which tend to repeat when the video input signal is of a given color television standard and tend to exhibit a pseudo-random distribution otherwise. A histogram processor provides a histogram of the measurements occurring within a given time interval and provides an output signal identifying standard and non-standard video input signal based on the histogram of the measurements.

Abstract: The present invention is directed to a video signal processing system including a burst locked clock generator which is repsonsive to separated chrominance signal provided by a comb filter. The comb filer includes apparatus responsive to a burst gate signal, for passing non-comb filtered video signal during burst intervals thereby enhancing the response time of the clock generator.

Abstract: An input filter separates a luminance input signal into a high frequency component that is noise reduced by coring and a low frequency component that is noise reduced by a frame recursive filter preceded by sub-sampling and followed by sample rate restoration by interpolation. An output circuit combines the noise reduced components to provide a processed output signal in which high frequency portions thereof are subjected to coring and low frequency portions thereof are subjected to recursive filtering. In a specific application the frame recursive filter provides a plurality of low frequency sub-sampled components which are combined with the processed output signal in a further output circuit to provide a noise reduced output signal of progressive scan form.

Abstract: An input filter separates a luminance input signal into a high frequency component that is noise reduced by coring and a low frequency component that is noise reduced by a frame recursive filter preceded by sub-sampling and followed by sample rate restoration by interpolation. An output circuit combines the noise reduced components to provide a processed output signal in which high frequency portions thereof are subjected to coring and low frequency portions thereof are subjected to recursive filtering. In a specific application the frame recursive filter provides a plurality of low frequency sub-sampled components which are combined with the processed output signal in a further output circuit to provide a noise reduced output signal of progressive scan form.

Abstract: Clamping circuitry for adjusting the D.C. voltage of a signal which is A.C. coupled to an ADC includes D.C. level adjusting circuitry coupled to the input of the ADC. Logic circuitry, responsive to a single bit of output samples provided by the ADC, provides control signals to the D.C. level adjusting circuitry, to condition the D.C. level adjusting circuitry to adjust the D.C. level of the A.C. signal to a desired value.

Abstract: An oscillator includes a mechanical resonator, such as a crystal, and having an amplifier arranged for oscillating at a first frequency. A resonant circuit is coupled in series with the crystal. The resonant circuit is antiresonant at an undesired harmonic frequency of the crystal thus prohibiting oscillation of the oscillator at said undesired harmonic frequency. The present oscillator is a portion of a phase locked loop used in a television receiver for demodulating a composite stereophonic audio signal.

Abstract: A circuit for receiving a video signal with a horizontal synchronizing component at a horizontal scanning frequency generates an intermediate synchronizing signal synchronized with the horizontal synchronizing component. A horizontal deflection circuit generates horizontal deflection current synchronized with the intermediate synchronizing signal. An oscillator generates a display locked clock signal synchronously with a clock synchronizing signal derived from the horizontal deflection current. A counter divides the clock signal, producing decodable outputs. A decoding circuit generates display locked timing signals, at the frequency of the horizontal synchronizing component and at the frequency of the intermediate signal, from the outputs of the counter.

Abstract: A digital-to-analog converter includes a sampled data sigma-delta modulator to resample and coarsely quantize the digital samples to be converted. The coarsely quantized samples are converted to sequences of pulses which are applied to a pulse sensitive analog integrator to develop analog representations of the digital signal.

Abstract: A bit-serial integrator includes the cascade combination of a bit-serial adder, a first bit-serial register and a second bit-serial register. Input signal is applied to one input of the adder and the output terminal of the second bit-serial register is coupled to a second input of the adder. A transparent latch is coupled to an output of the first bit-serial register and is conditioned to pass a predetermined number of sample bits and then to latch and output a particular sample bit for the duration of a sample period. The output of the latch is an integrated, scaled and truncated representation of the input signal.

Abstract: A video memory system which uses dynamic digital data storage elements allows random access to blocks of 32 pixel values. The pixel values to be stored in a block are applied sequentially to the memory system and the pixel values provided by the memory system are provided sequentially. The block oriented random access memory which stores and provides the blocks of 32 pixel values is configured to be able to perform a block read, a block write and a refresh operation in the time required to provide one 32 pixel block to or from the video memory system.

Abstract: A dual port digital memory system, which includes integral memory sequencing circuitry, is controlled by a bit-serial address and control signal. The address and control signal, which includes a data read address, a data write address and a control value, is serially loaded into a shift register. The address sequencing circuitry loads the read and write address values into integral read and write address registers and, based on the control value, initiates respective read and/or write operations.

Abstract: An antialias filtering and subsampling system incorporates a compound accumulator including three cascade connected accumulator circuits conditioned to integrate and dump the integrated values of n input samples. The integrated values from the three integrators are scaled, delayed and combined to produce substampled values of a signal which has been filtered according to the transfer function [sin(n.pi.ft)/nsin(.pi.ft)].sup.3.

Abstract: A sampled data treble control system, requiring a single multiplier element, includes the cascade connection of a first adder, the multiplier, and a second adder coupled between the system input and output terminals. A subtracter develops the differences between the system input and output signals and applies them to an Infinite Impulse Response filter. The filtered differences are scaled and coupled to the first and second adders. The system transfer function H(Z) is given byH(Z)=[1+(Z+1)/(1+1/A)K]/1+(Z-1)/(1+A)K]wherein A is a treble control variable applied to the multiplier, K is a scaling constant and Z is the conventional Z-transform variable.