Abstract: An input signal to an amplifier is coupled to a gate electrode of a first PMOS transistor operating as a common source inverting amplifier. The drain electrode of the first transistor is coupled to the source electrode of a second PMOS transistor via a junction terminal. An output signal is developed at the drain electrode of the second transistor. The junction terminal is coupled to a gate electrode of a third PMOS transistor, operating as a common source inverting amplifier. The drain electrode of the third transistor is coupled to the gate electrode of the second transistor for maintaining the drain voltage of the first transistor substantially constant when the input signal changes that maintains the output impedance at the drain electrode of the second transistor high.

Abstract: A sampled data tone control system, applicable for providing audio bass cut and boost control, includes a single variable multiplying circuit for determining the system variable response characteristics. Input samples are coupled to the multiplier which has its output connected to an integrator. The integrated samples are scaled by a constant and combined with the input samples to provide tone controlled signal.

Abstract: A variable preemphasis/deemphasis network is disclosed which is coupled between audio input and output terminals. The network exhibits a family of transfer function response characteristics which vary between a full deemphasis characteristic H(f) and a full emphasis characteristic 1/H(f) in response to a control signal and exhibits complementary transfer function response characteristics in response to reciprocal valued control signals. The network includes a signal filter which determines the shape of the transfer function response characteristic, and a gain controlled amplifier which determines which one of the family of transfer function response characteristics is exhibited in response to the control signal.

Abstract: Circuitry for calculating the square root of a binary number iterates the equation E(K+1)=E(K)+(S-E(K).sup.2) where E(K+1) is the current estimate of the square root of the sample S and E(K) is the previous estimate. The value E(K).sup.2 is estimated in order to reduce the complexity of the hardware. An application is described for real time processing of digital audio signals in serial-bit format.

Abstract: A volume control or amplitude varying system for digital signals includes a cascade connection of a coarse multiplier/divider for changing the values of digital signals in 6 db steps and a fine multiplier/divider for changing the values of digital values logarithmically in substantially equal steps of less than 6 db per step. The coarse multiplier/divider selectively multiplies the digital signal by powers of 2. The fine multiplier/divider multiplies the digital signal by predetermined values, an ascending/descending sequence of which form a substantially logarithmic sequence. Both serial-bit and parallel-bit embodiments are described.

Abstract: Pilot signal cancelling circuitry for removing the pilot signal from a composite signal, includes a subtraction circuit. The composite signal and a synthesized pilot signal are coupled to the minuend and subtrahend input connections of the subtraction circuit respectively. The output of the subtraction circuit is coupled to first and second multipliers. A cosine signal of like frequency to the pilot signal is applied to the first multiplier which develops a phase error signal. The phase error signal is coupled to an oscillator which develops the cosine signal. A sinusoidal signal, also developed by the oscillator and in phase with the pilot signal is applied to a second multiplier. The second multiplier generates a signal proportional to the amplitude of the residual pilot signal in the output signal provided by the subtraction circuit. The amplitude signal is multiplied by a sinusoid in phase with the pilot signal in a third multiplier to generate the synthesized pilot signal.

Abstract: A digital input signal to be delayed is applied to a two-point linear interpolation filter which imparts delay to the signal proportional to the value of a delay control signal. Errors in both the amplitude and the phase of the delayed signal are minimized by the addition of a correction signal to the delayed signal. The correction signal is provided by applying the input signal to a further filter and a multiplier connected in cascade. The further filter is a linear phase filter having a response zero at zero frequency and a delay equal to an add multiple of one-half of the sampling period, Ts, of the digital input signal. The multiplier is controlled so as to vary the amplitude of the compensating signal as a non-linear function of the delay control signal so as to provide maximum amplitude compensation at delays corresponding to odd multiples of Ts/2 and zero amplitude compensation at delays equal to integer multiples of Ts.

Abstract: A speed-up memory doubles the field rate of a video input signal by repeating each field to reduce flicker when the double field rate signal is displayed. Read/write clocks for controlling the memory are locked to the color subcarrier of the video input signal thereby tending to produce visual artifacts in the displayed image due to clock skew relative to sync when non-standard video signals are processed. The skew errors are corrected by circuitry which measures the skew of the read and write clocks and delays the video signal as a function of a difference between the clock skew measurements.

Abstract: In memory-based video signal processing systems such as frame recursive filters, for example, system performance is dependent upon critical timing relationships between incoming signals and delayed signals produced from the memory. Video signal from various sources, e.g. VTR's, tend to have jittering time bases that generally have prevented the use of such memory-based processing systems. The jittering signals may be standardized, in sampled data format, by effecting adaptive signal delays responsive to a measure of the relative phase of the sampling clock with respect to horizontal synchronizing pulses. The phase measure is used to control an interpolator which combines successive samples in proportions to develop sample values that should have occurred at the sample times had the signal not been jittering.

Abstract: A pix-in-pix television display includes a memory for holding samples representing one field of the small picture. Samples which are to be written into the memory are developed in a buffer memory one line at a time over intervals corresponding to the three line periods of the signal which produces the small picture. A line of samples is written from the buffer memory into the field memory over three line periods of the small picture signal. The memory write operation is suspended when data is read from the field memory for display. The write operation resumes when a read operation is completed at the address and pixel value which were being written when the write operation was suspended.

Abstract: A pix-in-pix television display includes circuitry for reducing the amount of memory needed to hold one field of the reduced size image. In the display apparatus, digital samples representing the large and small picture signals are developed at substantially equal rates by separate circuitry. Subsampling circuitry stores one out of every five of the samples representing a horizontal line of the small picture. These samples are displayed, synchronous with the large picture at a rate three-fifths times the display rate of the large picture samples to produce an apparent size reduction of one-third in the horizontal direction.

Abstract: A pix-in-pix display includes a filtering system for processing the video signals which produce the reduced-size image. The filtering system includes an anti-aliasing filter which reduces the amplitude of the components of the video signals which may cause aliasing distortion when the image is subsampled. However, the filter passes substantial amounts of these components. The filtered video signal is subsampled and applied to a peaking filter which amplifies the band of frequencies containing the aliasing components relative to lower frequency bands to improve the appearance of detailed portions of the reproduced image.

Abstract: System performance of picture-in-picture video display systems is dependent on critical timing relationships between the incoming signals and the clock signals used to sample and display both the large picture and small picture signals. Video signals from various sources, e.g. VTR's, tend to have jittering time bases which may cause the small image to appear jagged or tilted. This distortion in the small image may be reduced by effecting adaptive signal delays in the small picture signal responsive to the relative phase of the system clock signal with respect to the horizontal synchronizing pulses of the large and/or small picture signal. One phase measure is used to control an interpolator which combines successive samples of the small picture signal in proportions to develop sample values corresponding to samples that would have occurred had the small picture signal been sampled by a clock properly aligned to the small picture horizontal synchronizing pulses.

Abstract: A television receiver/monitor includes a progressive scan processor including memories for time compressing a video input signal and doubling the line rate to reduce visible line structure when the double line-rate signal is displayed. The memories are controlled to provide a video compression factor (2.5:1) greater than the display line rate increase (2:1) to provide a display retrace time (10.8 micro-seconds) substantially equal to the blanking interval (11.0 micro-seconds) of the video input signal thereby decreasing display power losses and horizontal drive requirements.

Abstract: Plural phase detectors in a progressively scanned television receiver measure the phase of the receiver video speed-up memory read and write clocks with respect to the double line-rate horizontal sweep signal of the display. Delay means are provided for delaying the video signal recovered from the memory as a function of the difference between the read and write clock phase measurements each time the memory is read. The delay is effective for minimizing visible artifacts which otherwise may tend to occur when displaying "non-standard" video signals wherein the ratio of the color-subcarrier frequency to the line-frequency of the incoming video signal differs from a given broadcasting standard.

Abstract: A system for controlling the speed of a brushless DC motor includes a microprocessor for generating stator control drive signals responsive to Hall sensors detecting relative rotor-pole-stator positions. Hall sensor signal transistions are compared against a reference frequency to provide an error signal which is processed by the microprocessor in accordance with a transfer function to emulate a type II servo loop. Stator commutation control signals are reduced in duration proportional to the resulting processed error signal. The control signals are thereafter applied to integrating current drives energizing the stator coils with triangular current signals.

Abstract: Direct current isolation and A.C. power line voltage reduction are provided in a first D.C. power supply by means of transformer coupling and in a second D.C. power supply by means of capacitor coupling which, additionally, provides suppression of differential mode and common mode components of high frequency noise or RF signals which may be present on the A.C. power line. The primary winding in the transformer coupled supply is switched and the D.C. output voltages produced by the supplies are combined to form a resultant bias signal of a first polarity and having relatively high current capability when the switch is closed, the bias signal being of a second polarity and having relatively limited current capability when the switch is open whereby high A.C. to D.C. conversion efficiency is achieved for either condition of the power switch.

Abstract: RF switching diodes in the antenna transfer switch of a video disc player are reverse biased by means of a bias supply when the main power supply of the player is turned off. The reverse bias counteracts any tendency for RF signals applied to the player antenna input connector from forward biasing the diodes which otherwise could result in intermodulation distortion of antenna input signals coupled to the player RF output connector. The effect of the reverse bias is augmented by a high pass filter in the antenna transfer switch which attenuates RF input signals at frequencies below the lowest assigned television channel frequency.

Abstract: In a system for recording digital information on a video disc and for playback of the digital information therefrom, the digital data is recorded in synchronism with the color subcarrier signal on a horizontal line adjacent to a constant luminance line. This arrangement facilitates a video disc player having a simple, efficient, video-to-digital interface for separating the prerecorded digital information from the video signal. The player apparatus is responsive to the color subcarrier signal and the chrominance-related output signal of a comb filter, both of which are normally available during video signal processing. Prerecorded digital information representing field number and type of program content is used by a microprocessor controller to provide player features such as locked groove detection, program elapsed time display, and end of program indication.

Abstract: The envelope of an input signal to be expanded is detected and applied via an adaptive filter to the gain control input of a variable gain device which expands the input signal. The adaptive filter provides improved ripple reduction and transient response characteristics and comprises a low pass filter for producing a smoothed control signal and an analog gate for coupling the greater of the smoothed control signal or a further signal to the variable gain device, the further signal being equal to the filter input signal less two predetermined constants. The gate further includes plural current paths selectively enabled for different conditions of the low pass filter input and output signals for augmenting the supply of current to the filter.