Abstract: Methods and systems for determining system lifetime characteristics are described. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.

Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.

Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.

Abstract: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.

Abstract: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.

Abstract: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.

Abstract: The present disclosure relates to wear leveling memory using error rate. A number of embodiments comprise: programming data to a selected group of a number of groups of memory cells based, at least partially, on a process cycle count corresponding to the selected group; determining an error rate corresponding to the selected group; and adjusting the process cycle count corresponding to the selected group based, at least partially, on the determined error rate corresponding to the selected group.

Abstract: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.

Abstract: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.

Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.

Abstract: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.

Abstract: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.

Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.

Abstract: Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.

Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.

Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.

Abstract: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.

Abstract: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.

Abstract: Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.

Abstract: Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.