Patents by Inventor Todd P. Albertson

Todd P. Albertson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11340258
    Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Joseph D. Stanford, David Craig, Todd P. Albertson, Mohit Mamodia, Dingying Xu
  • Patent number: 11112430
    Abstract: A probe head may be utilized to test an electronic device. The probe head may include a probe axis extending along a length of the probe head. The probe head may include a probe core including a first metal. The probe core may include a core surface having a first dimension. The first dimension may be perpendicular to the probe axis. The probe core may include a probe tip, for instance extending from the core surface along the probe axis. The probe tip has a second dimension that may be perpendicular to the probe axis. The second dimension may be less than the first dimension of the core surface. The probe head may include a cladding layer that includes a second metal. The cladding layer may be coupled around a perimeter of the probe core. The probe tip may extend beyond the cladding layer.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Anil Kaza, Donald E. Edenfeld, Todd P. Albertson, Patrick Whiting
  • Publication number: 20200309818
    Abstract: A probe head may be utilized to test an electronic device. The probe head may include a probe axis extending along a length of the probe head. The probe head may include a probe core including a first metal. The probe core may include a core surface having a first dimension. The first dimension may be perpendicular to the probe axis. The probe core may include a probe tip, for instance extending from the core surface along the probe axis. The probe tip has a second dimension that may be perpendicular to the probe axis. The second dimension may be less than the first dimension of the core surface. The probe head may include a cladding layer that includes a second metal. The cladding layer may be coupled around a perimeter of the probe core. The probe tip may extend beyond the cladding layer.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Inventors: Anil Kaza, Donald E. Edenfeld, Todd P. Albertson, Patrick Whiting
  • Publication number: 20200209280
    Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: Joseph D. Stanford, David Craig, Todd P. Albertson, Mohit Mamodia, Dingying Xu
  • Patent number: 10598696
    Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Joseph D. Stanford, David Craig, Todd P. Albertson, Mohit Mamodia, Dingying Xu
  • Patent number: 9977054
    Abstract: Etching for probe wire tip is described particularly well suited to microelectronic device test. In one example, wires of a probe head are covered with an encapsulation material, the wires being attached to a test probe head substrate, each of the wires having two ends, the first end being attached to the substrate and the second end being opposite the substrate, each wire having an outer coating around a core. The wires are etched to remove the outer coating at the second end of the wires. The encapsulation material is then removed.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Todd P. Albertson, David M. Craig, David Shia, Joseph D. Stanford
  • Patent number: 9823273
    Abstract: Probe tip formation is described for die sort and test. In one example, the tips of wires of a test probe head are prepared for use as test probes. The wires are attached to a test probe head substrate. The end opposite the substrate has a tip. The tips of the wires are polished when attached to the test probe head to form a sharpened point.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Keith J. Martin, Kip P. Stevenson, Kamil S. Salloum, Todd P. Albertson
  • Publication number: 20170276700
    Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.
    Type: Application
    Filed: March 28, 2016
    Publication date: September 28, 2017
    Inventors: Joseph D. Stanford, David Craig, Todd P. Albertson, Mohit Mamodia, Dingying Xu
  • Patent number: 9581639
    Abstract: Electronic device assemblies and methods including an organic substrate based space transformer are described. One assembly includes a space transformer comprising an organic substrate. The assembly also includes a carrier on which the space transformer is positioned, and a clamp positioned to couple the space transformer to the carrier. The assembly also includes a probe array positioned on the space transformer, wherein the space transformer is positioned between the probe array and the carrier. The assembly also includes a printed circuit board, wherein the carrier is positioned between the printed circuit board and the space transformer. The assembly also includes electrical connections to electrically couple the space transformer to the printed circuit board. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2013
    Date of Patent: February 28, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jin Yang, Erkan Acar, Todd P. Albertson, Joe F. Walczyk
  • Patent number: 9535095
    Abstract: Wire probes are described that resist rotation during assembly into a probe head of a die tester. One example includes probe wires with a protrusion at a pre-determined position along the length of the wire. A probe substrate with pads on one side each to attach to and electrically connect with a probe wire and a pads on the opposite side to connect to test equipment and a probe holder above the substrate with holes. Each hole holds a respective one of the probe wires against the probe substrate. Each hole also has a key to mate with a protrusion of a respective probe wire so that the protrusions engage the keys to prevent rotation of the respective wire.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: David Shia, Todd P. Albertson, Keith J. Martin
  • Publication number: 20160363613
    Abstract: Etching for probe wire tip is described particularly well suited to microelectronic device test. In one example, wires of a probe head are covered with an encapsulation material, the wires being attached to a test probe head substrate, each of the wires having two ends, the first end being attached to the substrate and the second end being opposite the substrate, each wire having an outer coating around a core. The wires are etched to remove the outer coating at the second end of the wires. The encapsulation material is then removed.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Applicant: INTEL CORPORATION
    Inventors: TODD P. ALBERTSON, DAVID M. CRAIG, DAVID SHIA, JOSEPH D. STANFORD
  • Publication number: 20160274148
    Abstract: An examples includes a substrate, including a conductive trace and a layer disposed on top of the conductive trace, the layer defining at least one cavity extending to the conductive trace and an electrical probe disposed in the cavity, with solder coupling the electrical probe to the conductive trace. The electrical probe can include a high yield strength wire core including a refractory metal and a thin oxidation protection layer concentrically disposed around high yield strength wire core and providing an outside surface of the electrical probe, the thin oxidation protection layer including predominantly one or more materials selected from gold, platinum, ruthenium, rhodium, palladium, osmium, iridium, chromium, and combinations thereof, wherein the solder fills the cavity and is coupled to the electrical probe inside the cavity, disposed between the electrical probe and the layer.
    Type: Application
    Filed: May 26, 2016
    Publication date: September 22, 2016
    Inventors: Kip Stevenson, Todd P. Albertson, David Shia, Kamil Salloum
  • Publication number: 20160178663
    Abstract: A test die contactor is described with a formed wire probe interconnect. In one example the contactor includes a plurality of wire probes formed to be resilient against longitudinal pressure, a first aligner proximate one end of the wire probes having a first plurality of holes through which the wire probes extend, the first alignment layer to align the wire probes to contact pads of a text fixture, a second aligner proximate the other end of the wire probes having a second plurality of holes through the wire probes extend, the second alignment layer to align the wire probes to contact pads of a device under test, and an insulating layer between the first and the second aligner through which the wire probes extend to hold the wire probes when compressed by longitudinal pressure.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Mohanraj Prabhugoud, Youngseok Oh, Joseph F. Walczyk, Todd P. Albertson
  • Patent number: 9354273
    Abstract: An examples includes a substrate, including a conductive trace and a layer disposed on top of the conductive trace, the layer defining at least one cavity extending to the conductive trace and an electrical probe disposed in the cavity, with solder coupling the electrical probe to the conductive trace. The electrical probe can include a high yield strength wire core including a refractory metal and a thin oxidation protection layer concentrically disposed around high yield strength wire core and providing an outside surface of the electrical probe, the thin oxidation protection layer including predominantly one or more materials selected from gold, platinum, ruthenium, rhodium, palladium, osmium, iridium, chromium, and combinations thereof, wherein the solder fills the cavity and is coupled to the electrical probe inside the cavity, disposed between the electrical probe and the layer.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Kip Stevenson, Todd P. Albertson, David Shia, Kamil Salloum
  • Patent number: 9279854
    Abstract: A mechanism is described for facilitating and employing a modular processing cell framework according to one embodiment. A method of embodiments may include accepting one or more semiconductor devices in one or more media at a modular processing cell framework (“framework”) including a plurality of test cells, moving the one or more semiconductor devices from the one or more media to one or more test cells for testing; and testing the one or more semiconductor devices.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: John C. Johnson, Eric J. Moret, Robert W. Edmondson, Todd P. Albertson
  • Patent number: 9255945
    Abstract: Methods and structures for testing a microelectronic packaging structure/device are described. Those methods may include placing a device in a floating carrier, wherein the floating carrier is coupled to a socket housing by pin dowels disposed in four corners of the socket housing, and wherein at least two actuating motors are disposed within the socket housing, and micro adjusting the device by utilizing a capacitive coupled or a fiber optic alignment system wherein a maximum measured capacitance or maximum measured intensity between alignment structures disposed in the socket housing and alignment package balls disposed within the device indicate optimal alignment of the device. Methods further include methods for active co-planarity detection through the use of a capacitive-coupled techniques.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Abram M. Detofsky, Todd P. Albertson, David Shia
  • Patent number: 9207258
    Abstract: An electrical probe of an aspect includes a high yield strength wire core. The high yield strength wire core includes predominantly one or more materials selected from tungsten, tungsten-copper alloy, tungsten-nickel alloy, beryllium-copper alloy, molybdenum, stainless steel, and combinations thereof. The high mechanical strength wire core has a yield strength of at least 1 gigapascal (GPa) at temperature of 250° C. The electrical probe also includes a low electrical resistivity layer concentrically around the high yield strength wire core. The concentric layer includes predominantly one or more materials selected from silver, gold, copper, and combinations thereof. The low electrical resistivity layer has an electrical resistivity of no more than 2×10?8 Ohm-meters. The electrical probe has an outer cross-sectional dimension of the electrical probe that is no more than 50 micrometers. Between 60 to 85% of the outer cross-sectional dimension is provided by the high mechanical strength wire core.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: David Shia, Todd P. Albertson, Kip P. Stevenson
  • Patent number: 9134343
    Abstract: An apparatus includes a robot and a sort probe gripper. The sort probe gripper includes a body, a jaw mount inserted into the body, a plurality of grippers mounted in the jaw mount and an actuator sleeve slidable along the body to engage the plurality of grippers.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 15, 2015
    Assignee: Intel Corporation
    Inventors: David Shia, Todd P. Albertson
  • Publication number: 20150185252
    Abstract: Electronic device assemblies and methods including an organic substrate based space transformer are described. One assembly includes a space transformer comprising an organic substrate. The assembly also includes a carrier on which the space transformer is positioned, and a clamp positioned to couple the space transformer to the carrier. The assembly also includes a probe array positioned on the space transformer, wherein the space transformer is positioned between the probe array and the carrier. The assembly also includes a printed circuit board, wherein the carrier is positioned between the printed circuit board and the space transformer. The assembly also includes electrical connections to electrically couple the space transformer to the printed circuit board. Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2013
    Publication date: July 2, 2015
    Inventors: Jin YANG, Erkan ACAR, Todd P. ALBERTSON, Joe F. WALCZYK
  • Patent number: 9069014
    Abstract: A wire probe assembly and forming process is described. In one example, a method includes inserting a plurality of wires through a probe former and a tip retainer to contact a probe head substrate, attaching the wires to a surface of the substrate, pulling the probe former laterally with respect to the substrate surface and the tip retainer to bend the wires into test probes with a resiliency to transverse movement, and removing the tip retainer to form a test probe head.
    Type: Grant
    Filed: June 30, 2012
    Date of Patent: June 30, 2015
    Assignee: Intel Corporation
    Inventors: Todd P. Albertson, Michael T. Crocker, David Shia, Lothar R. Kress