Patents by Inventor Todd P. Albertson

Todd P. Albertson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150061713
    Abstract: Wire probes are described that resist rotation during assembly into a probe head of a die tester. One example includes probe wires with a protrusion at a pre-determined position along the length of the wire. A probe substrate with pads on one side each to attach to and electrically connect with a probe wire and a pads on the opposite side to connect to test equipment and a probe holder above the substrate with holes. Each hole holds a respective one of the probe wires against the probe substrate. Each hole also has a key to mate with a protrusion of a respective probe wire so that the protrusions engage the keys to prevent rotation of the respective wire.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Inventors: David Shia, Todd P. Albertson, Keith J. Mortin
  • Publication number: 20150002181
    Abstract: Probe tip formation is described for die sort and test. In one example, the tips of wires of a test probe head are prepared for use as test probes. The wires are attached to a test probe head substrate. The end opposite the substrate has a tip. The tips of the wires are polished when attached to the test probe head to form a sharpened point.
    Type: Application
    Filed: June 29, 2013
    Publication date: January 1, 2015
    Inventors: Keith J. Martin, Kip P. Stevenson, Kamil S. Salloum, Todd P. Albertson
  • Patent number: 8891235
    Abstract: A thermal interface unit includes a pedestal, a first contact surface below the pedestal to interface with a first die and a flat spring to enable the first contact surface to adapt to a variable height of a first die of a multi-chip package (MCP).
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: November 18, 2014
    Assignee: Intel Corporation
    Inventors: Joseph F. Walczyk, Jin Yang, James G. Maveety, Todd P. Albertson, Ashish Gupta, Jin Pan, Arun Krishnamoorthy
  • Publication number: 20140218061
    Abstract: Methods and structures for testing a microelectronic packaging structure/device are described. Those methods may include placing a device in a floating carrier, wherein the floating carrier is coupled to a socket housing by pin dowels disposed in four corners of the socket housing, and wherein at least two actuating motors are disposed within the socket housing, and micro adjusting the device by utilizing a capacitive coupled or a fiber optic alignment system wherein a maximum measured capacitance or maximum measured intensity between alignment structures disposed in the socket housing and alignment package balls disposed within the device indicate optimal alignment of the device. Methods further include methods for active co-planarity detection through the use of a capacitive-coupled techniques.
    Type: Application
    Filed: March 10, 2014
    Publication date: August 7, 2014
    Inventors: Abram M. Detofsky, Todd P. Albertson, David Shia
  • Publication number: 20140184255
    Abstract: A mechanism is described for facilitating and employing a modular processing cell framework according to one embodiment. A method of embodiments may include accepting one or more semiconductor devices in one or more media at a modular processing cell framework (“framework”) including a plurality of test cells, moving the one or more semiconductor devices from the one or more media to one or more test cells for testing; and testing the one or more semiconductor devices.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: JOHN C. JOHNSON, ERIC J. MORET, ROBERT W. EDMONDSON, TODD P. ALBERTSON
  • Publication number: 20140176172
    Abstract: An examples includes a substrate, including a conductive trace and a layer disposed on top of the conductive trace, the layer defining at least one cavity extending to the conductive trace and an electrical probe disposed in the cavity, with solder coupling the electrical probe to the conductive trace. The electrical probe can include a high yield strength wire core including a refractory metal and a thin oxidation protection layer concentrically disposed around high yield strength wire core and providing an outside surface of the electrical probe, the thin oxidation protection layer including predominantly one or more materials selected from gold, platinum, ruthenium, rhodium, palladium, osmium, iridium, chromium, and combinations thereof, wherein the solder fills the cavity and is coupled to the electrical probe inside the cavity, disposed between the electrical probe and the layer.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Kip Stevenson, Todd P. Albertson, David Shia, Kamil Salloum
  • Patent number: 8710858
    Abstract: Methods and structures for testing a microelectronic packaging structure/device are described. Those methods may include placing a device in a floating carrier, wherein the floating carrier is coupled to a socket housing by pin dowels disposed in four corners of the socket housing, and wherein at least two actuating motors are disposed within the socket housing, and micro adjusting the device by utilizing a capacitive coupled or a fiber optic alignment system wherein a maximum measured capacitance or maximum measured intensity between alignment structures disposed in the socket housing and alignment package balls disposed within the device indicate optimal alignment of the device. Methods further include methods for active co-planarity detection through the use of a capacitive-coupled techniques.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: April 29, 2014
    Assignee: Intel Corporation
    Inventors: Abram M Detofsky, Todd P Albertson, David Shia
  • Publication number: 20140091821
    Abstract: An electrical probe of an aspect includes a high yield strength wire core. The high yield strength wire core includes predominantly one or more materials selected from tungsten, tungsten-copper alloy, tungsten-nickel alloy, beryllium-copper alloy, molybdenum, stainless steel, and combinations thereof. The high mechanical strength wire core has a yield strength of at least 1 gigapascal (GPa) at temperature of 250° C. The electrical probe also includes a low electrical resistivity layer concentrically around the high yield strength wire core. The concentric layer includes predominantly one or more materials selected from silver, gold, copper, and combinations thereof. The low electrical resistivity layer has an electrical resistivity of no more than 2×10?8 Ohm-meters. The electrical probe has an outer cross-sectional dimension of the electrical probe that is no more than 50 micrometers. Between 60 to 85% of the outer cross-sectional dimension is provided by the high mechanical strength wire core.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: David Shia, Todd P. Albertson, Kip P. Stevenson
  • Publication number: 20140091828
    Abstract: A sort probe gripper includes a body, a jaw mount inserted into the body, a plurality of grippers mounted in the jaw mount and an actuator sleeve slidable along the body to engage the plurality of grippers.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: David Shia, Todd P. Albertson
  • Publication number: 20140002124
    Abstract: A wire probe assembly and forming process is described.
    Type: Application
    Filed: June 30, 2012
    Publication date: January 2, 2014
    Inventors: Todd P. Albertson, Michael T. Crocker, David Shia, Lothar R. Kress
  • Publication number: 20140002994
    Abstract: A thermal interface unit includes a pedestal, a first contact surface below the pedestal to interface with a first die and a flat spring to enable the first contact surface to adapt to a variable height of a first die of a multi-chip package (MCP).
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Joseph F. Walczyk, Jin Yang, James G. Maveety, Todd P. Albertson, Ashish Gupta, Jin Pan, Arun Krishnamoorthy
  • Publication number: 20130269173
    Abstract: An apparatus comprising a robot; an end effector coupled to the robot and configured to grasp or transfer a probe of a size for use in a probe card; and instructions stored on a machine readable medium coupled to the robot, the instructions comprising to configure the robot to transfer a probe to a probe card substrate or, where the probe is attached to a probe card substrate, to move the probe. A method comprising automatically transferring a probe to a probe card substrate in an assembly process or, where the probe is attached to a probe card substrate, moving the probe in a repair process; and after transferring or moving the probe, heating the probe with a heat source.
    Type: Application
    Filed: December 30, 2011
    Publication date: October 17, 2013
    Inventors: Todd P. Albertson, David M. Craig, Anil Kaza, David Shia
  • Publication number: 20120074975
    Abstract: Methods and structures for testing a microelectronic packaging structure/device are described. Those methods may include placing a device in a floating carrier, wherein the floating carrier is coupled to a socket housing by pin dowels disposed in four corners of the socket housing, and wherein at least two actuating motors are disposed within the socket housing, and micro adjusting the device by utilizing a capacitive coupled or a fiber optic alignment system wherein a maximum measured capacitance or maximum measured intensity between alignment structures disposed in the socket housing and alignment package balls disposed within the device indicate optimal alignment of the device. Methods further include methods for active co-planarity detection through the use of a capacitive-coupled techniques.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 29, 2012
    Inventors: Abram M. Detofsky, Todd P. Albertson, David Shia
  • Patent number: 7345495
    Abstract: The present application relates to apparatus and methods for burn-in and other diagnostics performed on integrated circuits. In one embodiment, the invention includes a plurality of sockets, each to hold an integrated circuit (IC), and coupling power to the respective IC from a remote power supply, a plurality of voltage detectors, each coupled to a socket to sense the voltage of the power coupled to the respective IC, and a plurality of remote voltage regulators, each coupled between the power supply and a respective socket, to receive the sensed voltage from the respective voltage detector and to adjust the voltage of the respective coupled power in accordance therewith.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: March 18, 2008
    Assignee: Intel Corporation
    Inventors: Daniel J. Dangelo, Todd P. Albertson, Hon Lee Kon, Jin Pan
  • Patent number: 6360544
    Abstract: A thermal control unit for regulating the temperature of a component or device under test is disclosed. The thermal control unit includes a three-dimensional control structure having a base member and an extension member extending from one surface of the base member to divide the base member into first and second portions. The base member has another surface to thermally couple to the device. The thermal control unit further includes at least one heat transfer assembly in thermal contact with the first portion of the base member and one face of the extension member and at least one other heat transfer assembly in thermal contact with the second portion of the base member and another face of the extension member.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: March 26, 2002
    Assignee: Intel Corporation
    Inventor: Todd P. Albertson