Abstract: An exemplary method of fabricating an integrated circuit can include depositing a reflective metal material layer over a layer of polysilicon, depositing an anti-reflective coating over the reflective metal material layer, trim etching the anti-reflective coating to form a pattern, etching the reflective metal material layer according to the pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating.

Abstract: A mask generation method can enhance clear field phase shift masks using a chrome border around phase 180 regions. An exemplary method involves identifying edges of a 180 degree phase pattern, expanding these edges, and merging the expansions with chrome. An alternative method involves oversizing and undersizing phase 180 data, taking the difference, and merging the difference with chrome. The chrome region on the phase mask can improve mask generation by allowing the chrome on the mask to fully define the quartz etch.

Abstract: A technique in which a first boundary region is added to the ends of phase zero (0) pattern defining polygons and a second boundary region is added to the ends of phase 180 pattern. This technique can improve line end pattern definition and improve the manufacturability and patterning process window. The added boundary region balances the light on both sides of the line ends, resulting in a more predictable final resist pattern.

Abstract: In a process for forming a photoresist mask, a photoresist layer is applied to a substrate. A silyated layer is formed in the photoresist layer. The features of the silyated area correspond to the features of a photoresist mask to be formed. The photoresist layer is then etched to form a photoresist base beneath the silyated area. The photoresist base is etched to remove material from its sides such that it becomes narrower than the silyated area. The silyated area is then removed, leaving a photoresist mask on the substrate.

Abstract: A mask generation method can enhance clear field phase shift masks using a chrome border around phase 180 regions. An exemplary method involves identifying edges of a 180 degree phase pattern, expanding these edges, and merging the expansions with chrome. An alternative method involves oversizing and undersizing phase 180 data, taking the difference, and merging the difference with chrome. The chrome region on the phase mask can improve mask generation by allowing the chrome on the mask to fully define the quartz etch.

Abstract: A technique in which a first boundary region is added to the ends of phase zero (0) pattern defining polygons and a second boundary region is added to the ends of phase 180 pattern. This technique can improve line end pattern definition and improve the manufacturability and patterning process window. The added boundary region balances the light on both sides of the line ends, resulting in a more predictable final resist pattern.

Abstract: A technique in which a boundary region is added to the outside parallel edge of phase zero (0) pattern defining polygons. This technique can reduce the need for optical proximity correction (OPC) and improve the manufacturability and patterning process window for integrated circuits. The technique can also set the width of both phase 0 and phase 180 polygons to specific sizes, making OPC easier to assign.

Abstract: A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.

Abstract: An apparatus and method for detecting an endpoint for an etching process utilize a reaction chamber with an ion source and detector placed within the reaction chamber. The ion source directs a primary beam of ions towards a wafer so that the ion beam impacts the top layer of the wafer. A detector detects primary ions reflected from the wafer and secondary ions scattered from the wafer. A value is determined that corresponds to the amount of reflected and scattered ions. A change in the value indicates that the ion beam is impacting a layer beneath the top layer of the wafer, and signifies the reaching of the etch process endpoint.

Abstract: A method and apparatus for replacing dense via arrays in shrunk, electronic device designs involves identifying vias on the same node within the electronic device design. Once vias are identified as on the same node, the combined area of the vias is calculated. Based upon the combined area of the identified vias, a determination of how many new, larger vias to create is made. New vias that are larger than the originally identified vias are created in such a number that the total area of the new vias at least equals the combined area of the originally identified vias. The new via array, having greater spacing between individual vias than the original via array, is used to replace the original via array within the electronic device design.

Abstract: A method of making a semiconductor device is provided. A polysilicon layer is formed over a substrate and a metal layer is formed on the polysilicon layer. The metal layer and the polysilicon layer are annealed to form a metal silicide layer on the polysilicon layer. The metal silicide layer is patterned and the polysilicon layer is then patterned using the patterned metal silicide layer as a mask. The patterned metal silicide and polysilicon layers may be used as a gate electrode of a MOSFET.

Abstract: In a method for forming a connection structure in an integrated circuit, a first conducting material is deposited over a substrate and patterned to form a conducting stud in electrical contact with a conducting element of the substrate. A dielectric is formed over the substrate and the conducting stud. A trench is formed in the dielectric to expose a top portion of the conducting stud, and a second conducting material is inlaid in the trench to form wiring in electrical contact with the conducting stud. The electrically conducting element of the substrate may be an element of a semiconductor device or a wiring, contact or via. The first conducting material may be aluminum, and the second conducting material may be copper. The dielectric may be formed as a single layer and may be an organic low-k dielectric. Related connection structures are also disclosed.

Abstract: A method utilizing a multilayer anti-reflective coating layer structure. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating.

Abstract: A method of forming features on a semiconductor device uses sidewall spacers, and includes providing a sidewall template having first and second sidewall regions. A spacer layer of a spacer material is formed over the sidewall template. The spacer layer is then etched in a first etch to remove a first region of the spacer layer over the first sidewall region while leaving a second region of the spacer layer over the second sidewall region. The spacer layer is again etched in a second etch to for at least one sidewall spacer.

Abstract: A method of manufacturing a semiconductor structure, including etching an opening in a hard mask layer including a trench pattern width a first portion having a first width and a second portion being an oversized trench portion having a second width greater than a width of the first portion, the second portion being formed over a predetermined via location. Also including are steps of depositing a resist and patterning a via pattern in the predetermined via location, etching a via corresponding to the via pattern through the resist and at least partially through a dielectric layer, and etching an oversized trench portion corresponding to a second portion opening in the hard mask.

Abstract: A method for making frontside contact to a substrate through an SOI structure thereon is provided. An etching step is undertaken to form a trench in the SOI structure so as to expose and define a rug surface of the substrate. Then, a thin insulating layer, for example SiO2, is formed over the exposed surface of the substrate, this insulating layer being irregular because of its formation over the relatively rough etched surface. Contact material is provided in the trench, and electrical potential is applied across the contact and substrate sufficient to increase the conductivity of the insulating layer, i.e., to break down the insulating layer. Nitrogen may be implanted into the exposed surface of the substrate to slow subsequent growth of the insulating layer, resulting in an even thinner insulating layer, i.e., one even less resistant to breakdown upon application of electrical potential thereacross.

Abstract: A method of forming features on a semiconductor device uses sidewall spacers, and includes providing a sidewall template having first and second sidewall regions. A spacer layer of a spacer material is formed over the sidewall template. The spacer layer is then etched in a first etch to remove a first region of the spacer layer over the first sidewall region while leaving a second region of the spacer layer over the second sidewall region. The spacer layer is again etched in a second etch to for at least one sidewall spacer.

Abstract: A method of forming either a gate pattern or a line pattern in a resist by using a dark field mask and a combination of a negative photoresist and a positive photoresist. The dark field mask is used to create a hole within the positive photoresist, by exposing only a portion of the positive photoresist to light, and then by subjecting the positive photoresist to a developer. The negative photoresist is formed within the hole of the positive photoresist, and etched or polished so that it is only disposed within the hole. The negative photoresist and the positive photoresist are subjected to a flood light exposure, and then to a developer. This causes the positive photoresist to dissolve, leaving the negative photoresist, thereby providing a very-small-dimension resist pattern that can be used to form either a gate or a line for a semiconductor device.

Abstract: A method for making frontside contact to a substrate through an SOI structure thereon is provided. An etching step is undertaken to form a trench in the SOI structure so as to expose and define a rough surface of the substrate. Then, a thin insulating layer, for example SiO2 is formed over the exposed surface of the substrate, this insulating layer being irregular because of its formation over the relatively rough etched surface. Contact material is provided in the trench, and electrical potential is applied across the contact and substrate sufficient to increase the conductivity of the insulating layer, i.e., to break down the insulating layer. Nitrogen may be implanted into the exposed surface of the substrate to slow subsequent growth of the insulating layer, resulting in an even thinner insulating layer, i.e., one even less resistant to breakdown upon application of electrical potential thereacross.

Abstract: A method of forming a small contact hole uses a bright field mask to form a small cylinder in a positive resist layer. A negative resist layer is formed around the small cylinder, and then etched or polished back to leave a top portion of the small cylinder exposed above the negative resist layer. The negative resist layer and the small cylinder (positive resist) are flood exposed to light, and then subject to a developer. What remains is a small contact hole located where the small cylinder was previously located.