Abstract: A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.

Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: DRAM cell arrays having a cell area of less than about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.

Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.

Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.

Abstract: DRAM cell arrays having a cell area of less than about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: DRAM cell arrays having a cell area of about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.

Abstract: DRAM cell arrays having a cell area of less than about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.

Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: DRAM cell arrays having a cell area of about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.

Abstract: DRAM cell arrays having a cell area of less than about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2 DRAM devices.