Abstract: DRAM cell arrays having a cell area of less than about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A select gate of a NAND memory array has a first dielectric layer formed on a semiconductor substrate. A first conductive layer is formed on the first dielectric layer. Conductive spacers are formed on sidewalls of the first conductive layer and are located between an upper surface of the first conductive layer and the first dielectric layer. A second dielectric layer overlies the first conductive layer and the conductive spacers. A second conductive layer is formed on the second dielectric layer. A third conducive layer is formed on the second conductive layer, passes though a portion of the second conductive layer and the second dielectric layer, and contacts the first conductive layer. The third conductive layer electrically connects the first and second conductive layers.

Abstract: DRAM cell arrays having a cell area of less than about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal silicide. A transistor gate isolation capping layer is formed in the trench and on the metal silicide. Optional trench spacers can be added to reduce the critical dimension restraints of a given fabrication process and thus form a transistor having smaller feature sizes than the critical dimension.

Abstract: Apparatus and methods are provided. Floating-gate memory cells and select gates of NAND memory arrays are formed concurrently by anisotropically removing portions of a second conductive layer disposed on a first conductive layer such that remaining portions of the second conductive layer self align with and are disposed on sidewalls of the first conductive layer. The first conductive layer is disposed on a first dielectric layer that is disposed on a substrate. A second dielectric layer is formed overlying the first conductive layer and the remaining portions of the second conductive layer. A third conductive layer is formed on the second dielectric layer. A fourth conductive layer is formed on the third conductive layer. For the select gate, the fourth conductive layer also passes through the third conductive layer and the second dielectric layer to electrically connect the conductive layers.

Abstract: A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.

Abstract: A conductive structure for gate lines and local interconnects in microelectronic devices. The conductive structure can be used in memory cells for SRAM devices or other types of products. The memory device cell can comprise a first conductive line, a second conductive line, a first active area, a second active area, a third active area, and a fourth active area. The first conductive line includes a first gate, a second gate, a first contact and a second contact. The second conductive line includes a third gate, a fourth gate, a third contact and a fourth contact. The first active area is electrically coupled to the first gate and the third contact; the second active area is electrically coupled to the second gate and the fourth contact; the third active area is electrically coupled to the third gate and the first contact; and the fourth active area is electrically coupled to the fourth gate and the second contact. The memory cell device, for example, can be a cell for an SRAM device.

Abstract: NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array. A second gate stack is formed on a second dielectric layer that is formed on the substrate adjacent the first dielectric layer. The second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent an end of the NAND string. The second dielectric layer is thicker than the first dielectric layer.

Abstract: The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2 DRAM devices.

Abstract: A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and semiconductor devices embodying the cells are also provided. In accordance with one embodiment of the present invention, a memory device cell layout is provided comprising four active areas positioned between selected ones of the gates and local interconnects associated with different damascene trenches of the device.

Abstract: A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material.

Abstract: A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material.

Abstract: A method is provided for forming damascene gates and local interconnects a single process. By combining the formation of a damascene gate and local interconnect into a single process, a low cost solution is provided, having the advantages of low resistance wordlines and reduced gate length while reducing or eliminating the local interconnect to gate contact resistance. Further, the present invention provides flexible layout of active area to form small memory cells based upon the damascene gate and local interconnect structure. As such, the present invention is particularly suited for the fabrication of SRAM memory devices.

Abstract: Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal silicide. A transistor gate isolation capping layer is formed in the trench and on the metal silicide. Optional trench spacers can be added to reduce the critical dimension restraints of a given fabrication process and thus form a transistor having smaller feature sizes than the critical dimension.

Abstract: Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

Abstract: According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region.

Abstract: A first dielectric layer is formed over a first transistor gate and a second transistor source/drain region. Contact openings are formed in the first dielectric layer to the first transistor gate and to the second transistor source/drain region. A second dielectric layer is formed over the first dielectric layer and to within the contact openings. The second dielectric layer is etched selectively relative to the first dielectric layer to form at least a portion of a local interconnect outline within the second dielectric layer to extend between the first transistor gate and the second transistor source/drain region. The etching removes at least some of the second dielectric layer within the contact openings. Conductive material is formed within the local interconnect outline within the second dielectric layer which electrically connects the first transistor gate with the second transistor source/drain region. Other aspects are disclosed.

Abstract: The method comprises forming a layer comprised of BPSG above a substrate and a plurality of transistors, forming a dielectric layer above the BPSG layer, the dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0, forming a plurality of openings in the dielectric layer and the BPSG layer, each of the openings allowing contact to a doped region of one of the transistors, and forming a conductive local interconnect in each of the openings. In another embodiment, the method comprises forming a layer comprised of BPSG above the substrate and between the transistors, forming a local interconnect in openings formed in the BPSG layer, reducing a thickness of the BPSG layer after the local interconnects are formed, and forming a dielectric layer above the BPSG layer and between the local interconnects, wherein the dielectric layer has a dielectric constant greater than approximately 6.0.

Abstract: A conductive structure for gate lines and local interconnects in microelectronic devices. The conductive structure can be used in memory cells for SRAM devices or other types of products. The memory device cell can comprise a first conductive line, a second conductive line, a first active area, a second active area, a third active area, and a fourth active area. The first conductive line includes a first gate, a second gate, a first contact and a second contact. The second conductive line includes a third gate, a fourth gate, a third contact and a fourth contact. The first active area is electrically coupled to the first gate and the third contact; the second active area is electrically coupled to the second gate and the fourth contact; the third active area is electrically coupled to the third gate and the first contact; and the fourth active area is electrically coupled to the fourth gate and the second contact. The memory cell device, for example, can be a cell for an SRAM device.

Abstract: A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and semiconductor devices embodying the cells are also provided. In accordance with one embodiment of the present invention, a memory device cell layout is provided comprising four active areas positioned between selected ones of the gates and local interconnects associated with different damascene trenches of the device.