Abstract: Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some aspects, an integrated circuit described herein may include a first pixel and a second pixel, wherein the first pixel is proximate the second pixel in a mirrored configuration. In some aspects, an integrated circuit described herein may include a first pixel and a second pixel that is proximate to the first pixel along a row direction, and a conductive line extending along a column direction that intersects with the row direction, wherein the conductive line is in electrical communication with a first component of the first pixel and a second component of the second pixel.

Abstract: Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some embodiments, an integrated circuit may comprise a photodetection region and a drain region electrically coupled to the photodetection region, and the photodetection region may be configured to induce an intrinsic electric field in a direction from the photodetection region to the drain region(s). In some embodiments, a charge storage region and the drain region may be positioned on a same side of the photodetection region. In some embodiments, at least one drain layer may be configured to receive incident photons and/or charge carriers via the photodetection region. In some embodiments, an integrated circuit may comprise a plurality of pixels and a control circuit configured to control a transfer of charge carriers in the plurality of pixels.

Abstract: Some aspects relate to integrated devices for obtaining timing and/or spectral information from incident light. In some embodiments, a pixel may include one or more charge storage regions configured to receive charge carriers generated responsive to incident photons from a light source, with charge carriers stored in the charge storage region(s) indicative of spectral and timing information. In some embodiments, a pixel may include regions having different depths, each configured to generate charge carriers responsive to incident photons. In some embodiments, a pixel may include multiple charge storage regions having different depths, and one or more of the charge storage regions may be configured to receive the incident photons and generate charge carriers therein. In some embodiments, a pixel may include an optical sorting element configured to direct at least some incident photons to one charge storage region and other incident photons to another charge storage region.

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates.

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates.

Abstract: In some aspects, a method of operating a magnetic resonance imaging system comprising a B0 magnet and at least one thermal management component configured to transfer heat away from the B0 magnet during operation is provided. The method comprises providing operating power to the B0 magnet, monitoring a temperature of the B0 magnet to determine a current temperature of the B0 magnet, and operating the at least one thermal management component at less than operational capacity in response to an occurrence of at least one event.

Abstract: Some embodiments relate to an integrated circuit, comprising: a pixel, comprising: a photodetection region; and a drain configured to discard charge carriers from within a semiconductor region of the pixel outside of the photodetection region. Some embodiments relate to an integrated circuit, comprising: a pixel, comprising: a photodetection region; and a drain configured to discard charge carriers from the photodetection region, wherein the drain comprises a semiconductor region and the semiconductor region is contacted by a metal contact. Some embodiments relate to an integrated circuit, comprising: a pixel, comprising: a photodetection region; and a drain configured to discard charge carriers from the photodetection region, wherein the drain comprises a semiconductor region that to which electrical contact is made through a conductive path that does not include a polysilicon electrode.

Abstract: Some aspects relate to integrated devices for obtaining timing and/or spectral information from incident light. In some embodiments, a pixel may include one or more charge storage regions configured to receive charge carriers generated responsive to incident photons from a light source, with charge carriers stored in the charge storage region(s) indicative of spectral and timing information. In some embodiments, a pixel may include regions having different depths, each configured to generate charge carriers responsive to incident photons. In some embodiments, a pixel may include multiple charge storage regions having different depths, and one or more of the charge storage regions may be configured to receive the incident photons and generate charge carriers therein. In some embodiments, a pixel may include an optical sorting element configured to direct at least some incident photons to one charge storage region and other incident photons to another charge storage region.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes a charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates.

Abstract: A hand-held bioanalytic instrument is described that can perform massively parallel sample analysis including single-molecule gene sequencing. The instrument includes a pulsed optical source that produces ultrashort excitation pulses and a compact beam-steering assembly. The beam-steering assembly provides automated alignment of excitation pulses to an interchangeable bio-optoelectronic chip that contains tens of thousands of reaction chambers or more. The optical source, beam-steering assembly, bio-optoelectronic chip, and coupling optics register to an alignment structure in the instrument that can form at least one wall of an enclosure and dissipate heat.

Abstract: A method for correcting nucleotide incorporation signals for fluid potential effects or disturbances arising in nucleic acid sequencing-by-synthesis includes: disposing a plurality of template polynucleotide strands in a plurality of defined spaces disposed on a sensor array, the template polynucleotide strands having a sequencing primer and a polymerase bound therewith; exposing the template polynucleotide strands to a series of flows of nucleotide species flowed through a fluid manifold, the fluid manifold comprising passages for flowing nucleotide species and a branch passage for flowing a solution, the branch passage comprising a reference electrode and a sensing electrode; obtaining a plurality of nucleotide incorporation signals corresponding to the plurality of defined spaces, the nucleotide incorporation signals having a signal intensity related to a number of nucleotide incorporations; and correcting at least some of the plurality of nucleotide incorporation signals for fluid potential effects or dis

Abstract: Methods and apparatus relating to FET arrays including large FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: Described herein are techniques for determining an illumination position on an integrated photodetector, as may be used within a fluorescence detection system. In some embodiments, such techniques may include determining an illumination position on an integrated photodetector based, at least in part, on a measurement of an amount of current output from a pixel of the integrated photodetector, the amount of current corresponding to an amount of excitation light (e.g., used for exciting fluorescence in a sample) that is received at the pixel. In some embodiments, such techniques may include measuring an amount of current output from one or more drain regions of one or more pixels of an integrated photodetector (e.g., regions used to draw away charge carriers corresponding to excitation light so as to not pollute collected charge carriers that correspond to fluorescence light to be detected).

Abstract: Apparatus and techniques for electrokinetic loading of samples of interest into sub-micron-scale reaction chambers are described. Embodiments include an integrated device and related apparatus for analyzing samples in parallel. The integrated device may include at least one reaction chamber formed through a surface of the integrated device and configured to receive a sample of interest, such as a molecule of nucleic acid. The integrated device may further include electrodes patterned adjacent to the reaction chamber that produce one or more electric fields that assist loading the sample into the reaction chamber. The apparatus may further include a sample reservoir having a fluid seal with the surface of the integrated device and configured to hold a suspension containing the samples.

Abstract: Described herein are techniques for determining an illumination position on an integrated photodetector, as may be used within a fluorescence detection system. In some embodiments, such techniques may include determining an illumination position on an integrated photodetector based, at least in part, on a measurement of an amount of current output from a pixel of the integrated photodetector, the amount of current corresponding to an amount of excitation light (e.g., used for exciting fluorescence in a sample) that is received at the pixel. In some embodiments, such techniques may include measuring an amount of current output from one or more drain regions of one or more pixels of an integrated photodetector (e.g., regions used to draw away charge carriers corresponding to excitation light so as to not pollute collected charge carriers that correspond to fluorescence light to be detected).

Abstract: Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some embodiments, an integrated circuit may comprise a photodetection region and a drain region electrically coupled to the photodetection region, and the photodetection region may be configured to induce an intrinsic electric field in a direction from the photodetection region to the drain region(s). In some embodiments, a charge storage region and the drain region may be positioned on a same side of the photodetection region. In some embodiments, at least one drain layer may be configured to receive incident photons and/or charge carriers via the photodetection region. In some embodiments, an integrated circuit may comprise a plurality of pixels and a control circuit configured to control a transfer of charge carriers in the plurality of pixels.

Abstract: Apparatus and techniques for electrokinetic loading of samples of interest into sub-micron-scale reaction chambers are described. Embodiments include an integrated device and related apparatus for analyzing samples in parallel. The integrated device may include at least one reaction chamber formed through a surface of the integrated device and configured to receive a sample of interest, such as a molecule of nucleic acid. The integrated device may further include electrodes patterned adjacent to the reaction chamber that produce one or more electric fields that assist loading the sample into the reaction chamber. The apparatus may further include a sample reservoir having a fluid seal with the surface of the integrated device and configured to hold a suspension containing the samples.