Patents by Inventor Tohru Furuyama
Tohru Furuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5148393Abstract: A semiconductor memory according to the present invention comprises a MOS dynamic semiconductor memory cell in which one terminal of a current path of one MOS transistor is connected to one capacitor element, the other terminal of the current path of the MOS transistor is connected to a bit line, and a gate electrode of the transistor is connected to a word line, wherein a substrate of the MOS transistor is not connected to a fixed potential terminal, and the potential of the substrate is switched and controlled so that the MOS transistor time-selectively becomes an enhancement type or a depletion type which can prevent a threshold voltage loss over time.Type: GrantFiled: July 6, 1989Date of Patent: September 15, 1992Assignee: Kabushiki Kaisha ToshibaInventor: Tohru Furuyama
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Patent number: 5138427Abstract: Since the power-supply and/or signal-transmission wiring layers connected to the semiconductor chip regions are formed, each individual integrated circuit can be burned in on the semiconductor wafer and, in other words, an integrated circuit can be burned in on a wafer level. The integrated circuit can thus be burned in at the end of a wafer process. An assembled semiconductor device is subjected to a high temperature or a high humidity, for checking the reliability of the assembled device.Type: GrantFiled: July 2, 1990Date of Patent: August 11, 1992Assignee: Kabushiki Kaisha ToshibaInventor: Tohru Furuyama
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Patent number: 5043597Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a semiconductor integrated circuit including the semiconductor substrate, a semiconductor chip having the semiconductor substrate and semiconductor integrated circuit, and a plurality of substrate bias generation circuits arranged on the semiconductor chip in such a manner as to derive substrate bias voltages from a power source voltage supplied from the exterior to the semiconductor chip and uniformly apply the substrate bias voltages over the entire the semicondutor substrate.Type: GrantFiled: June 18, 1990Date of Patent: August 27, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Tohru Furuyama, Hiroto Tanaka
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Patent number: 5023476Abstract: An integrated semiconductor device is disclosed which has a highly-integrated circuit formed on a substrate. A constant voltage generator is connected to the integrated circuit, for receiving an externally-supplied d.c. power supply voltage to produce a regulated d.c. voltage, the potential level of which is lower than the external power supply voltage and remains substantially constant irrespective of the external power supply voltage. A mode-change controller is connected in parallel with the voltage generator, for supplying the output d.c. voltage of the voltage generator to the integrated circuit as an internal power supply voltage in a normal operation mode. When the device is subjected to an accelerated test using an increased power supply voltage, a switching transistor is rendered conductive under the control of a control circuit, thereby allowing the external power supply voltage to be directly applied to the integrated circuit.Type: GrantFiled: January 23, 1989Date of Patent: June 11, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Yohji Watanabe, Tohru Furuyama
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Patent number: 5014245Abstract: A dynamic random access memory includes switching transistors connected between bit lines and a sensing amplifier. The switching transistors are made non-conductive during a first period. An internal write enable signal is supplied for a predetermined period to a data input circuit to write a data into a memory cell of the dynamic random access memory. The predetermined period is controlled to terminate after the termination of the first period at an early write mode.Type: GrantFiled: June 20, 1990Date of Patent: May 7, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyoshi Muroka, Takashi Ohsawa, Tohru Furuyama
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Patent number: 4967395Abstract: An amplitude limiting circuit is arranged in a DRAM with (1/2) VCC precharge to equalize an amplitude between a precharge voltage and an "H" level output of each pair of bit lines charged and discharged in an active cycle with an amplitude of the precharge voltage and an "L" level output of each pair of bit lines.Type: GrantFiled: January 31, 1989Date of Patent: October 30, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Yohji Watanabe, Tohru Furuyama
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Patent number: 4841483Abstract: The invention provides a semiconductor memory having a plurality of memory cells and a bit line connected to the memory cells comprising, the bit line being formed of a plurality of sub-bit lines, switch means for interconnecting and disconnecting the sub-bit lines, reference potential means for storing reference potentials, and sense amplifier means for comparing the output of an addressed memory cell with the reference potentials, whereby the memory is capable of storing n-valued data using n different storage potentials.Type: GrantFiled: December 9, 1987Date of Patent: June 20, 1989Assignee: Kabushiki Kaisha ToshibaInventor: Tohru Furuyama
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Patent number: 4833341Abstract: An integrated semiconductor device is disclosed which has a highly-integrated circuit formed on a substrate. A constant voltage generator is connected to the integrated circuit, for receiving an externally-supplied d.c. power supply voltage to produce a regulated d.c. voltage, the potential level of which is lower than the external power supply voltage and remains substantially constant irrespective of the external power supply voltage. A mode-change controller is connected in parallel with the voltage generator, for supplying the output d.c. voltage of the voltage generator to the integrated circuit as an internal power supply voltage in a normal operation mode. When the device is subjected to an accelerated test using an increased power supply voltage, a switching transistor is rendered conductive under the control of a control circuit, thereby allowing the external power supply voltage to be directly applied to the integrated circuit.Type: GrantFiled: March 30, 1987Date of Patent: May 23, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Yohji Watanabe, Tohru Furuyama
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Patent number: 4733374Abstract: A semiconductor memory device has N sense amplifiers each having first and second input terminals, N first memory cells, N second memory cells, N first bit lines each of which is connected to the first memory cells of the same column and connected to the first input terminal of one of the sense amplifiers, and N second bit lines each of which is connected to the second memory cells of the same column and connected to the second input terminal of one of the sense amplifiers. The first memory cells are formed in a first memory cell area and the second memory cells are formed in a second memory cell area arranged adjacent to the first memory cell area and on the same side as the first memory cell area with respect to the sense amplifiers.Type: GrantFiled: March 27, 1986Date of Patent: March 22, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Tohru Furuyama, Shigeyoshi Watanabe, Tatsuo Ikawa
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Patent number: 4697252Abstract: A dynamic type semiconductor memory device is disclosed, which comprises an n-type semiconductor layer, at least one memory cell having a capacitor for storing charges of an amount corresponding to a logic value and a first transistor having source and drain regions formed in the surface area of the p-type semiconductor layer and for transferring charges to and from the capacitor, a first drive circuit for applying a voltage to the gate of the first transistor through a word line, a second drive circuit for selectively applying a voltage of one of first and second levels through a bit line and the first transistor to the capacitor, and a bias circuit for applying a voltage to the substrate. The first transistor of the memory device is a p-channel transistor formed in the n-type semiconductor layer which is formed in the surface area of a p-type semiconductor layer. The bias circuit includes a charge pump section for setting the potential of the substrate at a third level lower than the first voltage.Type: GrantFiled: March 9, 1984Date of Patent: September 29, 1987Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Tohru Furuyama, Yukimasa Uchida
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Patent number: 4686456Abstract: A memory test circuit in which test data is simultaneously written into plural memory cells of a semiconductor memory device and then subsequently read from the plural memory cells to assure reliable operation of the memory device. A logical sum and a logical product are formed of the test data read out from the plural memory cells. The logical product and the logical sum are subjected to an exclusive-or operation, the result of which is indicative of whether or not the test data was correctly written into the memory cells.Type: GrantFiled: March 31, 1986Date of Patent: August 11, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Tohru Furuyama, Takashi Ohsawa
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Patent number: 4569036Abstract: A semiconductor dynamic memory device includes a plurality of memories, row decoders for selecting the row of the memories, column decoders for selecting the column of memories, and sense amplifier circuits connected to the memories, respectively. The dynamic memory device further has a driving circuit for selectively activating some of the sense amplifier circuits in accordance with the content of a predetermined bit of row address data supplied to the row decoders.Type: GrantFiled: February 28, 1983Date of Patent: February 4, 1986Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Syuso Fujii, Shozo Saito, Kenji Natori, Tohru Furuyama
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Patent number: 4404657Abstract: A semiconductor memory circuit includes a power supply terminal; a first MOS transistor; a second MOS transistor whose source, gate and drain are respectively connected to the source, drain and gate of the first MOS transistor; first and second resistors connected between the power supply terminal and the drains of the first and second MOS transistors; a data line; a word line; and a third MOS transistor whose current path is connected between the drain of the first MOS transistor and data line, and whose gate is connected to the word line. The semiconductor memory circuit further includes a write control line whose potential is set at a high level when a readout operation is effected. The sources of the first and second MOS transistors are jointly connected to the write control line.Type: GrantFiled: October 16, 1980Date of Patent: September 13, 1983Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Tohru Furuyama, Tetsuya Iizuka
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Patent number: 4398267Abstract: A plurality of memory cells are arranged on a semiconductor substrate in the matrix form. Each memory cell comprises a first MOS field effect transistor whose drain electrode is connected to a read bit line, and whose source electrode is connected to a read word line, and a second MOS field effect transistor whose source electrode is connected to the gate electrode of the first MOS field effect transistor, and whose drain electrode is connected to a write bit line, and whose gate electrode is connected to a write word line. The first MOS field effect transistor is formed in the surface region of the semiconductor substrate and the second MOS field effect transistor is formed of a polycrystalline silicon layer, which is deposited on the semiconductor substrate with an oxide layer interposed therebetween to act as the gate region of the first MOS field effect transistor.Type: GrantFiled: December 2, 1980Date of Patent: August 9, 1983Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventor: Tohru Furuyama
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Patent number: 4368529Abstract: A semiconductor matrix circuit includes first and second matrix arrays of semiconductor memory cells, a plurality of sense amplifiers each having a flip-flop circuit, a plurality of first bit lines each commonly connected to memory cells in the same row of the first matrix array and also connected respectively to first bi-stable output terminals of the flip-flop circuits, and a plurality of second bit lines each commonly connected to memory cells in the same row of the second matrix array and also connected respectively to second bi-stable output terminals of the flip-flop circuits. Switching MOS transistors are each connected between the first and second bi-stable output terminals of a corresponding one of the flip-flop circuits. After a reading operation, the first and second bit lines are selectively set to high and low potential levels V.sub.D and V.sub.S, and subsequently all the switching MOS transistors are rendered conductive to set the potential on all the bit lines to an intermediate level (V.sub.Type: GrantFiled: October 17, 1980Date of Patent: January 11, 1983Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventor: Tohru Furuyama