Abstract: A semiconductor device including an oscillation circuit includes a MISFET having a halo region formed on a semiconductor substrate and a plurality of MISFETs having no halo regions formed on the semiconductor substrate. Gate electrodes of the plurality of MISFETs having no halo regions are electrically connected to each other. The plurality of MISFETs having no halo regions is used in a pair transistor included in the oscillation circuit.

Abstract: A semiconductor substrate includes an n-type substrate region, an n-type first semiconductor region and a second semiconductor region disposed at different positions on the n-type substrate region, an n-type buried layer formed on the n-type first semiconductor region and on the second semiconductor region, a p-type third semiconductor region and a p-type fourth semiconductor region formed on the n-type buried layer and spaced apart from each other, and an n-type fifth semiconductor region that reaches an upper surface of the semiconductor substrate from the n-type buried layer. The n-type buried layer, the n-type first semiconductor region, and the n-type substrate region are present under the p-type third semiconductor region and the n-type fifth semiconductor region. A first transistor is formed in an upper portion of the p-type third semiconductor region, and a second transistor is formed in an upper portion of the p-type fourth semiconductor region.

Abstract: An electric fuse including a fuse body and a fuse pad has a lamination structure of a polysilicon film and a cobalt silicide film. In the fuse body, a first portion having a first thickness and a second portion having a second thickness are formed. The first thickness is smaller than the second thickness. The polysilicon film is formed such that a thickness of the polysilicon film in the first portion becomes smaller than a thickness of the polysilicon film in the second portion.

Abstract: A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.

Abstract: A semiconductor substrate has a surface and a convex portion projecting upward from the surface. An n-type drift region has a portion located in the convex portion. The n?-type drain region has a higher n-type impurity concentration than the n-type drift region, and is arranged in the convex portion and on the n-type drift region such that the n?-type drain region and a gate electrode sandwich the n-type drift region in plan view.

Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.

Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer, a semiconductor layers and a silicide layer. The insulating layer is formed on the semiconductor substrate. The semiconductor layer is formed on the insulating layer and includes a polycrystalline silicon. The silicide layer is formed on the semiconductor layer. The semiconductor layer has a first semiconductor part and a second semiconductor part. The first semiconductor part includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type. The second semiconductor part is adjacent the second semiconductor region. In a width direction of the first semiconductor part, a second length of the second semiconductor part is greater than a first length of the first semiconductor part. A distance between the first and second semiconductor regions is 100 nm or more in an extension direction in which the first semiconductor region extends.

Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.

Abstract: A semiconductor device includes a first insulating layer, an optical waveguide, a first slab portion, a second insulating layer, and a conductive layer. The optical waveguide is formed on the first insulating layer and has a first side surface and a second side surface. The first slab portion is adjacent to the first side surface. The second insulating layer is formed on the optical waveguide. The conductive layer is formed on the second insulating layer. The optical waveguide has a first conductivity type. The first slab portion has first portion, second portion and third portion. The first portion has a second conductivity type opposite to the first conductivity type. The second portion is located farther from the optical waveguide than the first portion and has a first conductivity type. The third portion is formed between the optical waveguide and the second portion and has the first conductivity type.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer, a semiconductor layers and a silicide layer. The insulating layer is formed on the semiconductor substrate. The semiconductor layer is formed on the insulating layer and includes a polycrystalline silicon. The silicide layer is formed on the semiconductor layer. The semiconductor layer has a first semiconductor part and a second semiconductor part. The first semiconductor part includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type. The second semiconductor part is adjacent the second semiconductor region. In a width direction of the first semiconductor part, a second length of the second semiconductor part is greater than a first length of the first semiconductor part. A distance between the first and second semiconductor regions is 100 nm or more in an extension direction in which the first semiconductor region extends.

Abstract: A semiconductor device includes a first insulating layer, an optical waveguide, a first slab portion, a second insulating layer, and a conductive layer. The optical waveguide is formed on the first insulating layer and has a first side surface and a second side surface. The first slab portion is adjacent to the first side surface. The second insulating layer is formed on the optical waveguide. The conductive layer is formed on the second insulating layer. The optical waveguide has a first conductivity type. The first slab portion has first portion, second portion and third portion. The first portion has a second conductivity type opposite to the first conductivity type. The second portion is located farther from the optical waveguide than the first portion and has a first conductivity type. The third portion is formed between the optical waveguide and the second portion and has the first conductivity type.

Abstract: A semiconductor device includes a substrate having a first surface and a second surface that have top and back relation, an insulating layer formed on the first surface of the substrate, and an optical waveguide formed on the insulating layer and formed of a semiconducting layer. A first opening is formed on the second surface of the substrate. The first opening overlaps the optical waveguide in plan view.

Abstract: A semiconductor device includes a substrate having a first surface and a second surface that have top and back relation, an insulating layer formed on the first surface of the substrate, and an optical waveguide formed on the insulating layer and formed of a semiconducting layer. A first opening is formed on the second surface of the substrate. The first opening overlaps the optical waveguide in plan view.

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract: The performances of a semiconductor device are improved. The semiconductor device includes an insulation layer, an optical waveguide part formed over the insulation layer, and including a p type semiconductor region and an n type semiconductor region formed therein, and an interlayer insulation film formed over the insulation layer in such a manner as to cover the optical waveguide part. At the first portion of the optical waveguide part, in a cross sectional view perpendicular to the direction of extension of the optical waveguide part, the n type semiconductor region is arranged at the central part of the optical waveguide part, and the p type semiconductor region is arranged in such a manner as to surround the entire circumference of the n type semiconductor region.

Abstract: The performances of a semiconductor device are improved. The semiconductor device includes an insulation layer, an optical waveguide part formed over the insulation layer, and including a p type semiconductor region and an n type semiconductor region formed therein, and an interlayer insulation film formed over the insulation layer in such a manner as to cover the optical waveguide part. At the first portion of the optical waveguide part, in a cross sectional view perpendicular to the direction of extension of the optical waveguide part, the n type semiconductor region is arranged at the central part of the optical waveguide part, and the p type semiconductor region is arranged in such a manner as to surround the entire circumference of the n type semiconductor region.

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract: A manufacturing method of a semiconductor device comprises a step of ion-implanting a P-type impurity at a first dose amount to form semiconductor regions that are low concentration semiconductor regions of a high breakdown voltage P-type transistor, and a step of ion-implanting a P-type impurity at a second dose amount to form P? semiconductor regions that are low concentration semiconductor regions of a low breakdown voltage P-type transistor and form a P-type impurity layer that is a resistance portion of a polysilicon resistor. The manufacturing method further comprises a resistance portion forming step in which a resistance portion of the polysilicon resistor is made thinner than terminal portions at both ends of the resistance portion, and the second dose amount is larger than the first dose amount.