Abstract: A high integration bipolar transistor operable at very high operating speed is disclosed. A semiconductor device of this invention has a semiconductor substrate of a first conductivity type, a buried impurity region formed on the substrate, and a bipolar transistor formed on the buried impurity region, wherein a plurality of monocrystalline active regions defined by the buried impurity region are isolated from each other by an element isolation insulator, the buried impurity region is connected to a graft region formed on the element isolation insulator at least at the side wall of the buried impurity region, and connected to a semiconductor element in a different active region via the graft region.

Abstract: A bipolar transistor comprises an n-type Si semiconductor body having a convex portion, an insulation film covering the surface of the semiconductor body other than the convex portion, and a p-type polycrystalline Si layer formed on the insulation film. A p-type region formed in the convex portion serves as an intrinsic base region, the polycrystalline Si layer serves as an extrinsic base region, an n-type region formed in the intrinsic base region serves as an emitter region, and the body serves as a collector region.

Abstract: A semiconductor device is disclosed, which includes bipolar transistor each having an emitter, base and collector formed inside each protruding portion of a semiconductor substrate, and trenches for device isolation. The bipolar transistor and the trench are spaced apart from each other by a predetermined spacing. According to this arrangement, the width of a base contact becomes uniform and any change of transistor characteristics can be prevented effectively.

Abstract: A semiconductor device includes a semiconductor layer provided above a pair of bipolar transistors formed in a surface region of a semiconductor body. Schottky barrier diodes and resistors are formed in the semiconductor layer. The pair of bipolar transistors, the Schottky barrier diodes and the resistors are electrically connected to constitute a bipolar memory. Since the Schottky barrier diodes and the resistors can be formed above the bipolar transistors, an area required for the memory cell can be made greatly small and the occurrence of an hindrance caused by .alpha. particles is minimal.

Abstract: A bipolar transistor capable of operating at high speeds. In a bipolar transistor designed for operation at high speeds, a polycrystalline silicon layer used as a base electrode effects is a contact area with respect to the base region which lacks precision or tends to increase. Further, when the transistor is formed in a small size, the ratio of the contact area with respect to the polycrystalline area increases, making it difficult to increase the operation speed. In order to reduce the contact area of the polycrystalline silicon layer, this invention deals with the structure in which the polycrystalline silicon layer is brought into contact with a portion near the edge of the convex semiconductor layer maintaining a small size and a high precision.

Abstract: A semiconductor device is constructed so that an insulation film is provided in regions other than a protruding portion of a substrate. A polycrystalline silicon layer and a metal silicide layer are formed over said insulation film to provide a multi-layer structure, and a take-out portion for at least one of the emitter, base, and collector members of a bipolar transistor provided in the mesa region is constituted by a film of this multi-layer structure. By virtue of the use of metal silicide together with the polycrystalline silicon, a very low resistance is achieved which enhances the device's operating speed. Further, the metal silicide is separated from the protruding portion of the substrate by a portion of the polycrystalline silicon to provide a smooth interface with the substrate. This smooth interface significantly reduces crystal defects in the single crystal substrate.

Abstract: A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

Abstract: A semiconductor device wherein a layer doped with impurities is provided between a buried layer and an epitaxial layer, said layer doped with impurities having a conductivity of the type opposite to that of said buried layer and said epitaxial layer, a reversely biasing voltage is applied across the buried layer and the layer doped with impurities, and side surfaces of the epitaxial layer are surrounded by an insulator.This helps effectively prevent the element formed in the epitaxial layer from being affected by .alpha.-particles and greatly improve reliability of the semiconductor device.

Abstract: A semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.

Abstract: The invention deals with a semiconductor device which comprises a semiconductor substrate of a first conductivity type, a semiconductor region formed on said substrate, and a first insulation film provided between said semiconductor region and said semiconductor substrate, wherein said semiconductor substrate is isolated by said insulation film from a polycrystalline silicon layer formed in the periphery of said semiconductor region thereby to reduce the parasitic capacitance, and wherein said insulation film is stretched and arranged on the lower side of said semiconductor region.

Abstract: A semiconductor device includes a first insulation film formed on a monocrystalline substrate and having an opening, a monocrystalline semiconductor layer formed so as to protrude into the first insulation film, and a conductive layer formed in contact with the side section of the monocrystalline semiconductor layer and extending over a second insulation film formed on the monocrystalline semiconductor layer.

Abstract: A composition comprising; (A) a basic amino acid salt of a higher aliphatic phosphate represented by the following formula (I): ##STR1## in which R.sub.1 is an alkyl or alkenyl group having from 12 to 22 carbon atoms, and (B) an .alpha.-monoalkyl glyceryl ether represented by the following formula (II): ##STR2## in which R.sub.2 is an alkyl group having from 12 to 24 carbon atoms. The composition provides an O/W type emulsion suitable for use as cosmetics which has a small viscosity decrease at a high temperature and a small viscosity increase at a low temperature, is stable during storage over a long period of time, provides good feelings and a moisture retaining effect on use to the skin, and yet has an excellent safety.

Abstract: A lateral bipolar transistor affording a good controllability for a base length is disclosed.In fabricating a lateral bipolar transistor by forming a single crystal column and disposing heavily doped polycrystalline regions on both sides of the column, contact surfaces between the single crystal column and the heavily doped polycrystalline regions are controlled by etching of an oxide film. The etching of the oxide film can provide a device of a precision higher than attained by controlling any other element.

Abstract: Disclosed herein is an emulsifying agent comprising (a) a partially or completely neutralized product, with a basic substance, of a phosphoric acid ester which contains a phosphoric acid monoester represented by the general formula (I) and a phosphoric acid diester represented by the general formula (II) from 100:0 to 70:30 molar ratio: ##STR1## wherein R.sub.1 and R.sub.4 represent individually a linear alkyl group or a linear alkenyl group of 10-22 carbon atoms or a branched alkyl group of 12-24 carbon atoms, R.sub.2 and R.sub.3 represent individually an ethylene group or a propylene group, and m and n represent individually a number of 0-30, and (b) a nonionic surfactant with HLB of 6 or less. Emulsified cosmetics comprising (a) the neutralized product of the phosphoric acid ester, (b) a nonionic surfactant with HLB of 6 or less, (c) an oily substrate, and (d) water is also disclosed.

Abstract: An I.sup.2 L type nonvolatile memory of this invention has a structure wherein a floating gate is disposed through an insulating film on the surface of a semiconductor layer in the vicinity of a base region of an NPN transistor in an I.sup.2 L. The I.sup.2 L type nonvolatile memory of this invention controls current to flow through the base region of the NPN transistor of the I.sup.2 L, by means of charges to be stored in the floating gate. That is, the collector output current of the NPN transistor of the I.sup.2 L is modulated in dependence on the presence or absence of a channel underneath the floating gate as is generated depending on the presence or absence of charges within the floating gate and the polarity of the charges. As a result, the variation of the base current appears as an output signal at a collector terminal of the NPN transistor of the I.sup.2 L, and data stored in the floating gate can be read out.

Abstract: A semiconductor IC device in which an N-type semiconductor layer is formed in a P-type semiconductor substrate; the N-type layer is divided by a P.sup.+ -type insulation region into plural island regions; and an IIL is formed in a first island region while an NPN transistor is formed in a second island region, wherein an N-type up-diffused layer is formed from the bottom of the first island region up while an N-type well region is formed from the surface of the first island region down, and N.sup.+ -type buried layers are formed near the bottoms of the first and the second island region.

Abstract: A differential amplifier circuit wherein one collector of the multicollector of each of first, second and third inverse NPN transistors is connected to a base of the corresponding transistor; the first and second transistors are used as differential input transistors; the other collector of each of the first and second transistors is connected to a PNP transistor serving as a load current source; and an output is derived through the third transistor connected to the second transistor.

Abstract: A current mirror circuit wherein an I.sup.2 L circuit is employed as the load of a current mirror circuit formed of a PNP (NPN) transistor, the injector of the I.sup.2 L circuit is common with those of another group of I.sup.2 L circuits, and a predetermined current is derived from the PNP (NPN) transistor of the current mirror circuit.