Patents by Inventor Tohru Okabe
Tohru Okabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10209592Abstract: An active matrix substrate includes an insulating substrate in which light-transmitting areas and a light-shielding area are formed. The active matrix substrate further includes: a light-shielding film formed in the light-shielding area on the insulating substrate, with a transparent base material containing carbon particles, the light shielding film being colored with the carbon particles; an inorganic film formed on the light-shielding film; light-transmitting films formed in the light-transmitting areas on the insulating substrate, with a transparent base material containing transparent oxidized carbon particles; gate lines provided on the inorganic film; a gate insulating film provided on the gate lines; thin film transistors provided in matrix on the gate insulating film; and data lines provided on the light-shielding film to intersect with the gate lines. The data lines are electrically connected with the thin film transistors.Type: GrantFiled: July 7, 2016Date of Patent: February 19, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Hara, Tomohiro Kosaka, Izumi Ishida, Shogo Murashige
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Publication number: 20180254293Abstract: An active matrix substrate 10 includes: an insulating substrate 110; a first conductive film 130 formed on the insulating substrate 110; a light-transmitting film 114 formed on the insulating substrate 110 so that the light-transmitting film 114 covers the first conductive film 130; a second conductive film 140 formed on the light-transmitting film 114; a first insulating layer 115 formed on the light-transmitting film 114 so that the first insulating layer 115 covers the second conductive film 140; a semiconductor film 170 formed on the first insulating layer 115; and a third conductive film 150 formed on the first insulating layer 115 and the semiconductor film 170. The first conductive film 130 and the second conductive film 140 are electrically connected via the third conductive film 150.Type: ApplicationFiled: September 7, 2016Publication date: September 6, 2018Inventors: TOHRU OKABE, HIROHIKO NISHIKI, TAKESHI HARA, TOMOHIRO KOSAKA, IZUMI ISHIDA, SHOGO MURASHIGE
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Publication number: 20180239127Abstract: A display device includes: a translucent substrate; a light-shielding film provided on the translucent substrate; first transparent insulating films that are provided on the translucent substrate so as to cover the covering the light-blocking film; and a plurality of thin film transistors (TFTs) that are provided on the first transparent insulation films and include a portion of lines made of conductive films. The light-shielding film is arranged so as to overlap at least the TFTs, when viewed in a direction vertical to the translucent substrate.Type: ApplicationFiled: August 31, 2015Publication date: August 23, 2018Applicant: Sharp Kabushiki KaishaInventors: Hirohiko NISHIKI, Tohru OKABE
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Publication number: 20180210306Abstract: An active matrix substrate includes an insulating substrate 100 in which light-transmitting areas and a light-shielding area are formed. The active matrix substrate further includes: a light-shielding film 201 formed in the light-shielding area on the insulating substrate 100, with a transparent base material containing carbon particles, the light shielding film being colored with the carbon particles; an inorganic film 202 formed on the light-shielding film; light-transmitting films 204 formed in the light-transmitting areas on the insulating substrate, with a transparent base material containing transparent oxidized carbon particles; gate lines 111 provided on the inorganic film; a gate insulating film 101 provided on the gate lines; thin film transistors 300 provided in matrix on the gate insulating film; and data lines provided on the light-shielding film to intersect with the gate lines. The data lines are electrically connected with the thin film transistors 300.Type: ApplicationFiled: July 7, 2016Publication date: July 26, 2018Applicant: SHARP KABUSHIKI KAISHAInventors: TOHRU OKABE, HIROHIKO NISHIKI, TAKESHI HARA, TOMOHIRO KOSAKA, IZUMI ISHIDA, SHOGO MURASHIGE
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Publication number: 20180188575Abstract: An active matrix substrate includes an insulating substrate (100); a surface coating film (110) that covers at least a part of a surface of the insulating substrate; an insulating light-transmitting film (204) provided on the insulating substrate including the surface coating film; gate lines; a gate insulating film; thin film transistors; data lines; and lead-out lines (115). In a peripheral portion of the insulating substrate, an area where the insulating light-transmitting film is not provided is formed. The lead-out line is provided so as to intersect with an outer circumference end of the insulating light-transmitting film, when viewed in a direction vertical to the insulating substrate. In the area where the insulating light-transmitting film is not provided, the surface coating film is also provided on a part in contact with the outer circumference end of the insulating light-transmitting film.Type: ApplicationFiled: July 7, 2016Publication date: July 5, 2018Inventors: TOMOHIRO KOSAKA, TAKESHI HARA, TOHRU OKABE, IZUMI ISHIDA, SHOGO MURASHIGE, KENICHI KITOH, HIROHIKO NISHIKI
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Patent number: 9716183Abstract: A semiconductor device includes a thin film transistor (100), the thin film transistor (100) including: a substrate (1); a gate electrode (3) provided on the substrate (1); a gate dielectric layer (5) formed on the gate electrode (3); an island-shaped oxide semiconductor layer (7) formed on the gate dielectric layer (5); a protective layer (9) provided so as to cover an upper face (7u) and an entire side face (7e) of the oxide semiconductor layer (7), the protective layer (9) having a single opening (9p) through which the upper face (7u) of the oxide semiconductor layer (7) is only partially exposed; and a source electrode (11) and a drain electrode (13) which are in contact with the oxide semiconductor layer (7) within the single opening (9p).Type: GrantFiled: March 10, 2015Date of Patent: July 25, 2017Assignee: SHARP KABUSHIKI KAISHAInventors: Hirohiko Nishiki, Akira Sasakura, Tohru Okabe
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Publication number: 20170018646Abstract: A semiconductor device includes a thin film transistor (100), the thin film transistor (100) including: a substrate (1); a gate electrode (3) provided on the substrate (1); a gate dielectric layer (5) formed on the gate electrode (3); an island-shaped oxide semiconductor layer (7) formed on the gate dielectric layer (5); a protective layer (9) provided so as to cover an upper face (7u) and an entire side face (7e) of the oxide semiconductor layer (7), the protective layer (9) having a single opening (9p) through which the upper face (7u) of the oxide semiconductor layer (7) is only partially exposed; and a source electrode (11) and a drain electrode (13) which are in contact with the oxide semiconductor layer (7) within the single opening (9p).Type: ApplicationFiled: March 10, 2015Publication date: January 19, 2017Inventors: Hirohiko NISHIKI, Akira SASAKURA, Tohru OKABE
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Patent number: 9519198Abstract: A liquid crystal display device, which includes: a liquid crystal layer; and a first substrate and a second substrate that are arranged so as to face each other with the liquid crystal layer being sandwiched therebetween. On the liquid crystal layer side of the first substrate, there are provided: a plurality of first thin film transistors that are arranged in a display region; a peripheral drive circuit which includes a plurality of second thin film transistors and is arranged in the periphery of the display region so as to supply drive signals to the plurality of first thin film transistors; an organic insulating film that is formed so as to cover the plurality of first thin film transistors and the plurality of second thin film transistors; and an inorganic insulating film that is formed on the organic insulating film.Type: GrantFiled: November 20, 2013Date of Patent: December 13, 2016Assignee: SHARP KABUSHIKI KAISHAInventors: Hirohiko Nishiki, Takeshi Hara, Tohru Okabe
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Publication number: 20160190181Abstract: A semiconductor device includes: a plurality of thin film transistors including a gate electrode, a gate dielectric layer, a semiconductor layer formed on the gate dielectric layer, and a source electrode and a drain electrode provided on the semiconductor layer; a source metal layer including a global line which supplies a common signal to the plurality of thin film transistors, the global line being made of the same electrically conductive film as the source electrode and drain electrode; and a dielectric protection layer covering the plurality of thin film transistors and the source metal layer. The source metal layer includes a lower layer and an upper layer stacked on a portion of the lower layer. The global line has a first layer structure including the lower layer and the upper layer, and at least a portion of each source electrode and of each drain electrode that is located on the semiconductor layer has a second layer structure including the lower layer but not including the upper layer.Type: ApplicationFiled: December 2, 2013Publication date: June 30, 2016Inventors: Naoki UEDA, Akihiro ODA, Hirohiko NISHIKI, Tohru OKABE
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Patent number: 9366933Abstract: An array board (a semiconductor device) 11b includes a display area TFT (a display area transistor) 17, a non-display area TFT (a non-display area transistor) 29, an upper insulator 31, and a lower insulator 30. The display area TFT 17 is arranged in a display area AA. The non-display area TFT 29 is arranged in a non-display area NAA. The upper insulator 31 is arranged in the non-display area NAA and formed from a second interlayer insulation film 41. The lower insulator 30 is arranged in the non-display area and formed from a first interlayer insulation film 39. The lower insulator 30 is arranged below the upper insulator 31 such that they are layered.Type: GrantFiled: September 13, 2013Date of Patent: June 14, 2016Assignee: Sharp Kabushiki KaishaInventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Hara, Kenichi Kitoh, Hisao Ochi
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Publication number: 20150286082Abstract: A liquid crystal display device, which includes: a liquid crystal layer; and a first substrate and a second substrate that are arranged so as to face each other with the liquid crystal layer being sandwiched therebetween. On the liquid crystal layer side of the first substrate, there are provided: a plurality of first thin film transistors that are arranged in a display region; a peripheral drive circuit which includes a plurality of second thin film transistors and is arranged in the periphery of the display region so as to supply drive signals to the plurality of first thin film transistors; an organic insulating film that is formed so as to cover the plurality of first thin film transistors and the plurality of second thin film transistors; and an inorganic insulating film that is formed on the organic insulating film.Type: ApplicationFiled: November 20, 2013Publication date: October 8, 2015Inventors: Hirohiko Nishiki, Takeshi Hara, Tohru Okabe
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Publication number: 20150241724Abstract: An array board (a semiconductor device) 11b includes a display area TFT (a display area transistor) 17, a non-display area TFT (a non-display area transistor) 29, an upper insulator 31, and a lower insulator 30. The display area TFT 17 is arranged in a display area AA. The non-display area TFT 29 is arranged in a non-display area NAA. The upper insulator 31 is arranged in the non-display area NAA and formed from a second interlayer insulation film 41. The lower insulator 30 is arranged in the non-display area and formed from a first interlayer insulation film 39. The lower insulator 30 is arranged below the upper insulator 31 such that they are layered.Type: ApplicationFiled: September 13, 2013Publication date: August 27, 2015Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Hara, Kenichi Kitoh, Hisao Ochi
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Publication number: 20150221677Abstract: The present invention provides an active matrix substrate including a thin film transistor that sufficiently achieves high reliability and a low capacitance, a production method for the active matrix substrate without an increase in the number of photomasks, a display device including the active matrix substrate, and a production method for the display device. The active matrix substrate of the present invention includes a thin film transistor that includes a semiconductor layer consisting of an oxide semiconductor. The active matrix substrate includes at least the semiconductor layer consisting of the oxide semiconductor, an etching stopper layer, and an interlayer insulating film formed from a spin-on-glass material. In the plan view of the principal surface of the substrate, the etching stopper layer covers at least part of the semiconductor layer, and the interlayer insulating film covers at least part of the etching stopper layer.Type: ApplicationFiled: September 17, 2013Publication date: August 6, 2015Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Hara, Kenichi Kitoh, Hisao Ochi
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Publication number: 20150214374Abstract: The present invention provides a circuit substrate and a display device in which oxide semiconductor layers that TFTs include are produced according to areas where the oxide semiconductor layers are present, whereby the reliability thereof is sufficiently enhanced. This circuit substrate is a circuit substrate obtained by arranging semiconductor elements on a transparent substrate, each of the semiconductor elements including an oxide semiconductor layer. The circuit substrate includes a protective film arranged above the semiconductor element, and an organic insulating film arranged above the protective film. The organic insulating films have openings above at least a part of oxide semiconductor layers.Type: ApplicationFiled: August 26, 2013Publication date: July 30, 2015Applicant: Sharp Kabushiki KaishaInventors: Takeshi Hara, Hirohiko Nishiki, Izumi Ishida, Tohru Okabe, Manabu Daio
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Patent number: 9087749Abstract: An active matrix substrate (20a) includes a gate electrode (25) formed on an insulating substrate (10a), and a planarizing film (26) formed on the gate electrode (25) and made of a baked SOG material. The gate electrode (25) is a multilayer film including a first conductive film (27) formed on the insulating substrate (10a) and made of a metal except copper, a second conductive film (28) formed on the first conductive film (27) and made of copper, and a third conductive film (29) formed on the second conductive film (28) and made of the metal except copper.Type: GrantFiled: December 20, 2011Date of Patent: July 21, 2015Assignee: Sharp Kabushiki KaishaInventors: Takeshi Hara, Hirohiko Nishiki, Hisao Ochi, Tetsuya Aita, Tohru Okabe, Yuya Nakano
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Patent number: 8823002Abstract: An object of this invention is to provide a semiconductor device in which TFTs with high mobility are arranged in both of display and peripheral circuit areas. A semiconductor device fabricating method according to the present invention includes the steps of: irradiating an amorphous silicon layer (34) with energy, thereby obtaining a microcrystalline silicon layer; and forming a doped semiconductor layer (35) on the amorphous silicon layer (34). In the step of irradiating, the amorphous silicon layer (34) is irradiated with energy that has a first quantity, thereby forming a first microcrystalline silicon layer (34A) including a channel layer for a first TFT (30A), and is also irradiated with energy that has a second quantity, which is larger than the first quantity, thereby forming a second microcrystalline silicon layer (34B) including a channel layer for a second TFT (30B).Type: GrantFiled: August 23, 2010Date of Patent: September 2, 2014Assignee: Sharp Kabushiki KaishaInventors: Michiko Takei, Tohru Okabe, Tetsuya Aita, Tsuyoshi Inoue, Yoshiyuki Harumoto, Takeshi Yaneda
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Patent number: 8810765Abstract: An electroluminescence element includes an electroluminescence substrate including a thin film transistor substrate, and a light-emitting layer provided over the thin film transistor substrate and divided by picture-element separating portions so as to correspond to unit picture elements; and a sealing substrate arranged to hermetically seal the light-emitting layer of the electroluminescence substrate. At least one of the electroluminescence substrate and the sealing substrate is a flexible substrate. Spacers are provided between the electroluminescence substrate and the sealing substrate.Type: GrantFiled: January 11, 2008Date of Patent: August 19, 2014Assignee: Sharp Kabushiki KaishaInventors: Tohru Okabe, Hirohiko Nishiki
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Publication number: 20140014950Abstract: An active matrix substrate (20a) includes a gate electrode (25) formed on an insulating substrate (10a), and a planarizing film (26) formed on the gate electrode (25) and made of a baked SOG material. The gate electrode (25) is a multilayer film including a first conductive film (27) formed on the insulating substrate (10a) and made of a metal except copper, a second conductive film (28) formed on the first conductive film (27) and made of copper, and a third conductive film (29) formed on the second conductive film (28) and made of the metal except copper.Type: ApplicationFiled: December 20, 2011Publication date: January 16, 2014Applicant: SHARP KABUSHIKI KAISHAInventors: Takeshi Hara, Hirohiko Nishiki, Hisao Ochi, Tetsuya Aita, Tohru Okabe, Yuya Nakano
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Patent number: 8582072Abstract: A method for manufacturing a display device 10 includes a substrate supporting step for supporting a plastic substrate 19 on a support substrate 50, with the plastic substrate 19 curved, and a thin film lamination step for laminating a plurality of thin films on the plastic substrate 19 supported on the support substrate 50.Type: GrantFiled: March 3, 2009Date of Patent: November 12, 2013Assignee: Sharp Kabushiki KaishaInventors: Tohru Okabe, Takeshi Hara, Tetsuya Aita, Tsuyoshi Inoue
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Patent number: 8530899Abstract: The present invention has an object of providing a TFT in which generation of an OFF current is reduced by an efficient manufacturing method. A thin film transistor 100 according to the present invention has a gate electrode 12 formed on a substrate 10, an insulating layer 14 formed on the gate electrode 12, a microcrystalline amorphous silicon layer 18 and an amorphous silicon layer 16 that are formed on the insulating layer 14, a semiconductor layer 20 containing an impurity formed on the amorphous silicon layer 16, and a source electrode 22A and a drain electrode 22B that are formed on the semiconductor layer 20 containing an impurity. The microcrystalline amorphous silicon layer 18 and the semiconductor layer 20 containing an impurity are connected to each other through the amorphous silicon layer 16 without being in direct contact with each other.Type: GrantFiled: December 21, 2010Date of Patent: September 10, 2013Assignee: Sharp Kabushiki KaishaInventors: Yoshiyuki Harumoto, Takeshi Hara, Tohru Okabe, Takeshi Yaneda, Tetsuya Aita, Tsuyoshi Inoue, Michiko Takei