Patents by Inventor Tohru Suzuki

Tohru Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Die
    Patent number: 12179250
    Abstract: The die includes a die base, a die body, and an opening/closing member. In the die base, a storage portion for storing refrigerant is formed. The die body includes a mounting surface, a forming surface, and a plurality of flow channels. The mounting surface is located on the storage portion side of the die base. The forming surface is located on the opposite side of the mounting surface. The flow channels pass through the die body from the mounting surface to the forming surface. The opening/closing member is disposed between the die base and the die body. The opening/closing member includes a plurality of through holes corresponding to the plurality of flow channels. The opening/closing member is configured to be movable with respect to the die base and the die body such that each of the through holes brings the corresponding flow channel and the storage portion into communication.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 31, 2024
    Assignee: NIPPON STEEL CORPORATION
    Inventors: Naruhiko Nomura, Toshiya Suzuki, Kenta Uenishi, Tohru Yoshida
  • Patent number: 12147192
    Abstract: A carrier for developing an electrostatic latent image is provided. The carrier comprises a core particle having an internal void ratio of from 0.0% to 2.0% and a coating layer coating the core particle. The coating layer contains flat chargeable particles satisfying Formula 1 blow: 1.0?R1/R2?3.0??Formula 1 where R1 [nm] and R2 [nm] represent a major axis and a thickness, respectively, of each of the flat chargeable particles. The carrier has an apparent density of from 2.0 to 2.5 g/cm3.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: November 19, 2024
    Assignee: Ricoh Company, Ltd.
    Inventors: Hiroyuki Kishida, Kousuke Suzuki, Tohru Suganuma, Minoru Masuda, Masashi Nagayama, Kento Takeuchi, Kaede Masuko
  • Publication number: 20240339460
    Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.
    Type: Application
    Filed: June 18, 2024
    Publication date: October 10, 2024
    Inventors: Kengo HARA, Tohru DAITOH, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Hitoshi TAKAHATA
  • Patent number: 12113758
    Abstract: A communication control apparatus according to one aspect of the present invention determines whether a message to be transmitted from an information processing apparatus include at least one attached file, when the message is transmitted from the information processing apparatus to one or more destinations via a network. When the communication control apparatus has determined that the message to be transmitted includes said at least one attached file, the communication control apparatus acquires approval of transmission of said at least one attached file from an approver, and transmits the message including said at least one attached file to said one or more destinations, on condition that approval of transmission of said at least one attached file has been received from the approver.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: October 8, 2024
    Assignee: NTT Communications Corporation
    Inventors: Tomonori Takada, Hideaki Akabori, Tsunechika Kishida, Yoshihiko Kobayashi, Masataka Suzuki, Tohru Minakuchi
  • Patent number: 12105472
    Abstract: A carrier for forming an electrophotographic image contains a core particle and a coating layer coating the core particle, wherein the coating layer contains a particle containing antimony and an anionic dispersant and the particle containing antimony includes a substrate particle containing a first inorganic fine particle.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: October 1, 2024
    Assignee: Ricoh Company, Ltd.
    Inventors: Kento Takeuchi, Masashi Nagayama, Tohru Suganuma, Tomomi Suzuki
  • Patent number: 12100711
    Abstract: An active matrix substrate includes a plurality of oxide semiconductor TFTs, and a plurality of wiring line connection sections, each of the plurality of wiring line connection sections includes a first connection electrode, an interlayer insulating layer extending over the first connection electrode, a wiring line contact hole formed in an insulating layer including the interlayer insulating layer, the wiring line contact hole exposing a part of a metal oxide layer of a first connection electrode, and a second connection electrode, and the second connection electrode is connected to a part of the metal oxide layer of the first connection electrode in the wiring line contact hole.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: September 24, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Tetsuo Kikuchi, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata, Tohru Daitoh
  • Publication number: 20240302763
    Abstract: An image forming method is provided that includes: developing an electrostatic latent image formed on an image bearer, with use of a developer containing a carrier and toner, the carrier having a core material particle and a covering layer, the covering layer covering the core material particle and containing an antimony-containing particle; and supplying the carrier to the developer.
    Type: Application
    Filed: February 26, 2024
    Publication date: September 12, 2024
    Inventors: Minoru MASUDA, Masashi NAGAYAMA, Tohru SUGANUMA, Kento TAKEUCHI, Tomomi SUZUKI
  • Publication number: 20240295834
    Abstract: A carrier contains a core material with a surface roughness Rz of from 2.0 to 3.0 ?m; and a coating layer to cover the core material, the coating layer comprising an antimony-containing particle.
    Type: Application
    Filed: March 1, 2024
    Publication date: September 5, 2024
    Inventors: Masashi NAGAYAMA, Kento TAKEUCHI, Tomomi SUZUKI, Tohru SUGANUMA
  • Publication number: 20240297181
    Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.
    Type: Application
    Filed: May 14, 2024
    Publication date: September 5, 2024
    Inventors: Masahiko SUZUKI, Tetsuo KIKUCHI, Hideki KITAGAWA, Setsuji NISHIMIYA, Kengo HARA, Hitoshi TAKAHATA, Tohru DAITOH
  • Patent number: 12056778
    Abstract: The confidentiality of data is maintained in a case where analysis of an operation state of a facility is entrusted to the outside. An embodiment of the present invention is configured to chronologically store log data in a first storage medium, and store attribute information indicating a relevance between a type of a failure expected to occur in a facility and each of a plurality of data users; The embodiment is further configured to select, at the occurrence of a failure in the facility, a data user who has a relevance to a type of the failure from among the plurality of data users based on the attribute information, selectively read log data relating to an operation state of the facility in which the failure has occurred, and transmits the read log data to the selected data user.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: August 6, 2024
    Assignee: NTT Communications Corporation
    Inventors: Tomonori Takada, Hideaki Akabori, Tsunechika Kishida, Yoshihiko Kobayashi, Masataka Suzuki, Tohru Minakuchi
  • Patent number: 12057454
    Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: August 6, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kengo Hara, Tohru Daitoh, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Hitoshi Takahata
  • Publication number: 20220365454
    Abstract: A mark detecting apparatus includes an imaging unit configured to generate an alignment mark image by imaging of an alignment mark on an object, a detecting unit configured to detect the alignment mark in the alignment mark image, and an adjusting unit configured to adjust a parameter relating to the imaging, based on a learning model generated by learning using the alignment mark image in which the alignment mark could not be detected and a first parameter as the parameter for the imaging of the alignment mark image in which the alignment mark could be detected. The adjusting unit acquires a second parameter as a result of inference processing based on the learning model. The imaging unit performs the imaging in a state where the parameter is adjusted to the second parameter.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 17, 2022
    Inventors: Masashi Yamamoto, Tohru Suzuki, Hisatoshi Neya, Yoshiaki Kurosawa, Shingo Yoneda, Masanori Hioki
  • Patent number: 10466602
    Abstract: A lithography apparatus detects a plurality of first substrate-side marks arranged with respect to a part of shot regions on which patterning is to be performed by using the first original in the lithography apparatus and detects a plurality of second substrate-side marks arranged with respect to other shot regions different from the part of the shot regions on which patterning is to be performed by using the second original different from the first original in another lithography apparatus. The lithography apparatus outputs information on detection results of the plurality of second substrate-side marks to be available in the other lithography apparatus. Then, based on detection results of the plurality of first substrate-side marks, the lithography apparatus performs patterning while performing alignment with the first original with respect to the part of the shot regions.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 5, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Taichi Yoshioka, Yusuke Kurita, Tohru Suzuki, Moritaka Iwakoshi, Taizou Kawada, Hironori Okazumi, Shunsuke Karaki, Takayuki Hashimoto
  • Publication number: 20190072864
    Abstract: A lithography apparatus detects a plurality of first substrate-side marks arranged with respect to a part of shot regions on which patterning is to be performed by using the first original in the lithography apparatus and detects a plurality of second substrate-side marks arranged with respect to other shot regions different from the part of the shot regions on which patterning is to be performed by using the second original different from the first original in another lithography apparatus. The lithography apparatus outputs information on detection results of the plurality of second substrate-side marks to be available in the other lithography apparatus. Then, based on detection results of the plurality of first substrate-side marks, the lithography apparatus performs patterning while performing alignment with the first original with respect to the part of the shot regions.
    Type: Application
    Filed: August 23, 2018
    Publication date: March 7, 2019
    Inventors: Taichi Yoshioka, Yusuke Kurita, Tohru Suzuki, Moritaka Iwakoshi, Taizou Kawada, Hironori Okazumi, Shunsuke Karaki, Takayuki Hashimoto
  • Patent number: 9647198
    Abstract: Piezoelectric oriented ceramics containing a Pb(Ti, Zr)O3-based compound having a high degree of orientation not lower than 0.64, which was calculated with the Lotgering method based on an X-ray diffraction pattern in a prescribed cross-section thereof, and having a sintered density not lower than 85% of a theoretical density.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: May 9, 2017
    Assignees: MURATA MANUFACTURING CO., LTD., NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Yasunari Miwa, Shinichiro Kawada, Masahiko Kimura, Tohru Suzuki, Tetsuo Uchikoshi, Yoshio Sakka
  • Patent number: 9356279
    Abstract: In a (001) pole figure of the active material particles, where a plane parallel to the substrate is defined as the equatorial plane, a Lotgering factor fa(001) of an A plane and a Lotgering factor fh(001) of a B plane satisfy both Expressions (1) and (2) below, the A plane being an equatorial cross section perpendicular to a line that connects the center of the (001) pole figure and a first point of maximum XRD intensity of peaks attributed to (001) planes at the outer periphery of the equatorial plane, the B plane being an equatorial cross section perpendicular to a line that connects the center of the (001) pole figure and a second point of minimum XRD intensity of peaks attributed to the (001) planes at the outer periphery of the equatorial plane: fa(001)>0.3 ??Expression (1) fa(001)?fb(001)<1.0 ??Expression (2).
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: May 31, 2016
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Masato Hozumi, Toshiya Saito, Hideto Yamada, Tohru Suzuki, Tetsuo Uchikoshi, Yoshio Sakka
  • Patent number: 9181557
    Abstract: The present invention provides uracil-requiring Moorella bacteria obtained by destroying a gene coding for orotidine-5-phosphate decarboxylase; and transforming-gene-introduced Moorella bacteria obtained by introducing a gene coding for orotidine-5-phosphate decarboxylase and a transforming-gene to a chromosome of the uracil-requiring Moorella bacteria. The present invention was accomplished by uracil-requiring Moorella bacteria, comprising an MTA-D-pF strain that is obtained by destroying a gene coding for orotidine-5-phosphate decarboxylase on a chromosome of Moorella bacteria.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: November 10, 2015
    Assignees: Mitsui Engineering & Shipbuilding Co., Ltd., Hiroshima University, Gifu University
    Inventors: Yutaka Nakashimada, Akihisa Kita, Tohru Suzuki, Shinsuke Sakai, Kazue Takaoka
  • Patent number: 8979560
    Abstract: A lever type connector in which workability in inserting terminals is enhanced is provided. A lever type connector 1 includes a connector housing 22 for containing terminals 61 at terminal ends of wires, and a lever 30 which is rotatably mounted on the connector housing 22, and rotated at a wire extending side of the connector housing 22 thereby to move a mating connector to be engaged with the connector housing 22 up to a normally engaged position. The lever 30 includes a pair of arm parts 31 (31a, 31b), and a connecting part 38 for interconnecting respective base end parts 51 (51a, 51b) of the arm parts 31. A recess part 53 for enlarging a distance between the base end parts 51 is provided on at least one of inner walls 50 (50a, 50b) of the base end parts 51 of the arm parts 31 which are opposed to each other.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 17, 2015
    Assignee: Yazaki Corporation
    Inventors: Tohru Kobayashi, Tohru Suzuki
  • Patent number: 8814581
    Abstract: A lever type connector in which workability in inserting terminals is enhanced is provided. A lever type connector 1 includes a connector housing 22 for containing terminals 61 at terminal ends of wires, and a lever 30 which is rotatably mounted on the connector housing 22, and rotated at a wire extending side of the connector housing 22 thereby to move a mating connector to be engaged with the connector housing 22 up to a normally engaged position. The lever 30 includes a pair of arm parts 31 (31a, 31b), and a connecting part 38 for interconnecting respective base end parts 51 (51a, 51b) of the arm parts 31. A recess part 53 for enlarging a distance between the base end parts 51 is provided on at least one of inner walls 50 (50a, 50b) of the base end parts 51 of the arm parts 31 which are opposed to each other.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: August 26, 2014
    Assignee: Yazaki Corporation
    Inventors: Tohru Kobayashi, Tohru Suzuki
  • Publication number: 20140206084
    Abstract: The present invention provides a primer set used for transformation that imparts a uracil requiring property by deleting or destroying a gene coding for orotidine-5-phosphate decarboxylase in Moorella bacteria. The present invention is accomplished by a primer set that is used for creating a uracil requiring strain obtained by deleting or destroying a gene coding for orotidine-5-phosphate decarboxylase in Moorella bacteria by homologous recombination and is represented by SEQ ID No. 1 and 2 that amplify an upstream region adjacent to said gene coding for orotidine-5-phosphate decarboxylase.
    Type: Application
    Filed: June 1, 2012
    Publication date: July 24, 2014
    Applicants: MITSUI ENGINEERING & SHIPBUILDING CO., LTD., GIFU UNIVERSITY, HIROSHIMA UNIVERSITY
    Inventors: Yutaka Nakashimada, Akihisa Kita, Tohru Suzuki, Shinsuke Sakai, Kazue Takaoka