Abstract: The present invention has an object to reduce the number of necessary masks to reduce manufacturing cost. A method of manufacturing a display device includes: forming electrodes or first lines; forming a first insulating film covering the electrodes or the first lines; forming a second insulating film covering the first insulating film; collectively forming first contact holes through the first insulating film and the second insulating film so as to expose parts of the electrodes or parts of the first lines; planarizing a surface of the second insulating film; and forming a first conductive layer to be connected from the surface of the second insulating film to the exposed parts of the electrodes or the exposed parts of the first lines via the first contact holes.

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer.

Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.

Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.

Abstract: A bearing raceway ring (25) disposed near a mounting section (9) is disposed on the outer periphery of a circular cylinder section (19). A fluid-sealed chamber (40) in which a measurement liquid is hermetically enclosed is provided between a first member (8) and the bearing raceway ring (25) which is disposed near the mounting section (9). Pressure acting on the fluid to be measured changes as the bearing raceway ring (25) moves in the cylinder-axis direction, the bearing raceway ring (25) being disposed near the mounting section (9). The fluid-sealed chamber (40) is provided with a pressure sensor (44) capable of detecting a change in the pressure of the fluid to be measured.

Abstract: In order to implement a structure capable of improving the resolution of torque measurement while preventing the plastic deformation of a torsion bar (15), an input-side stopper (61) having an uneven shape (gear shape) in the circumferential direction is provided in a portion of an input-side rotating body (55) that includes an input shaft (13) and an input gear (7), and an output-side stopper (63) having an uneven shape (gear shape) in the circumferential direction is provided in a portion of an output-side rotating body (56) that includes an output shaft (14) and an output gear (8). The input-side stopper (61) and the output-side stopper (63) are combined so as to be engaged to be able to transmit torque only when the torsional angle within the elastic range of the torsion bar (15) reaches a predetermined amount.

Abstract: In order to implement a structure capable of improving the resolution of torque measurement while preventing the plastic deformation of a torsion bar (15), an input-side stopper (61) having an uneven shape (gear shape) in the circumferential direction is provided in a portion of an input-side rotating body (55) that includes an input shaft (13) and an input gear (7), and an output-side stopper (63) having an uneven shape (gear shape) in the circumferential direction is provided in a portion of an output-side rotating body (56) that includes an output shaft (14) and an output gear (8). The input-side stopper (61) and the output-side stopper (63) are combined so as to be engaged to be able to transmit torque only when the torsional angle within the elastic range of the torsion bar (15) reaches a predetermined amount.

Abstract: A bearing residual life prediction method, a bearing residual life diagnostic apparatus and a bearing diagnostic system can be provided. The bearing diagnostic system 20 includes: an eddy current tester 11 that measures the impedance X of a certain portion of a bearing 24 before and after the use of the bearing; a bearing information transmitter 30 that transmits bearing information s1 containing the impedance X; and a bearing information receiver 31 that receives the information; a diagnostic section 12 that obtains the residual life information s2 of the bearing 24 based on the received impedance X; and a life information transmitter 36 that transmits the residual life information s2; and a life information receiver 40 that receives the information. Hence, the bearing used by the user can be inspected nondestructively, and the residual life of the bearing can be predicted.

Abstract: A bearing residual life prediction method, a bearing residual life diagnostic apparatus and a bearing diagnostic system can be provided. The bearing diagnostic system 20 includes: an eddy current tester 11 that measures the impedance X of a certain portion of a bearing 24 before and after the use of the bearing; a bearing information transmitter 30 that transmits bearing information s1 containing the impedance X; and a bearing information receiver 31 that receives the information; a diagnostic section 12 that obtains the residual life information s2 of the bearing 24 based on the received impedance X; and a life information transmitter 36 that transmits the residual life information s2; and a life information receiver 40 that receives the information. Hence, the bearing used by the user can be inspected nondestructively, and the residual life of the bearing can be predicted.

Abstract: A roughness of an outer ring raceway surface 14 formed on an inner peripheral surface of an outer ring 13 is made larger than a roughness of inner ring raceway surfaces 12a, 12b of an inner ring 11. Also, an average roughness Ra of the outer ring raceway surface 14 is set within 0.1 ?m?Ra?0.5 ?m in an axial direction and a circumferential direction in ranges of b1/(B/2)?0.9, b2/ (B/2)?0.9 and in a measured length of 0.1 mm to 1.0 mm where B is a width of the outer ring 13 and b1, b2 are a distance from both end surfaces of the outer ring 13 in the axial direction respectively. A roughness parameter S of the outer ring raceway surface is set within 0<S?20 ?m.

Abstract: A roughness of an outer ring raceway surface 14 formed on an inner peripheral surface of an outer ring 13 is made larger than a roughness of inner ring raceway surfaces 12a, 12b of an inner ring 11. Also, an average roughness Ra of the outer ring raceway surface 14 is set within 0.1 ?m?Ra?0.5 ?m in an axial direction and a circumferential direction in ranges of b1/(B/2)?0.9, b2/ (B/2)?0.9 and in a measured length of 0.1 mm to 1.0 mm where B is a width of the outer ring 13 and b1, b2 are a distance from both end surfaces of the outer ring 13 in the axial direction respectively. A roughness parameter S of the outer ring raceway surface is set within 0<S?20 ?m.

Abstract: The problem is to provide a technology to reduce a light leakage current in order to obtain a good display. One kind or plurality kinds of elements chosen from argon, germanium, silicon, helium, neon, krypton, and xenon are implanted in a crystalline semiconductor layer, to distribute crystal defects due to the aforementioned element implantation by uniform and suitable density in the semiconductor film, making recombination centers of carriers, to thereby suppress alight sensitivity without spoiling a high degree of carrier movement included in a crystalline semiconductor layer.

Abstract: A liquid crystal display device includes an active matrix substrate; a counter substrate; and a liquid crystal layer interposed between the active matrix substrate and the counter substrate. The active matrix substrate includes a plate; a thin film transistor provided on the plate; and a side light shielding layer for covering at least a portion of a side surface of the thin film transistor.

Abstract: The problem is to provide a technology to reduce a light leakage current in order to obtain a good display. One kind or plurality kinds of elements chosen from argon, germanium, silicon, helium, neon, krypton, and xenon are implanted in a crystalline semiconductor layer, to distribute crystal defects due to the aforementioned element implantation by uniform and suitable density in the semiconductor film, making recombination centers of carriers, to thereby suppress alight sensitivity without spoiling a high degree of carrier movement included in a crystalline semiconductor layer.

Abstract: The active matrix substrate of the invention includes: a storage capacitor formed on a board; a first insulating layer formed on the storage capacitor; a semiconductor layer formed above the storage capacitor via the first insulating layer: a gate insulating layer formed on the semiconductor layer; a gate electrode layer including a gate electrode formed above the semiconductor layer via the gate insulating layer; a second insulating layer covering the gate electrode layer and the semiconductor layer; a first light-shielding layer formed above the semiconductor layer via the second insulating layer to cover at least a channel region of the semiconductor layer; a third insulating layer formed on the first light-shielding layer; a source electrode layer including source and drain electrodes formed on the third insulating layer; a fourth insulating layer formed on the source electrode layer; and a pixel electrode formed on the fourth insulating layer and electrically connected to the drain electrode.

Abstract: The invention involves: the forming of a dummy pattern for planarization between convex portions (for example, between lead electrodes and a signal wire pattern) of irregularities caused by a patterned layer on a surface on which at least one interlayer insulating film is formed, so as to be separated by a predetermined distance from the convex portions; the forming of interlayer insulating films 7a-7d so as to fill up gaps between the dummy pattern and the convex portions; and the planarizing of a surface. Thereby, the invention is capable of relaxing requirements on uniformity in the thickness of the film to be polished and the thickness of the polished portion.

Abstract: An active matrix substrate of the present invention has a substrate, a thin-film transistor and a capacitive element provided on the principal plane of the substrate, and a scanning line for supplying a scanning signal to the thin-film transistor, in which the thin-film transistor has a semiconductor layer including a channel region and a gate electrode formed on the semiconductor layer. The capacitive element is located at a position opposite to the substrate at the both sides of the thin-film transistor. The scanning line is formed by a conductive layer different from the gate electrode and located at a position closer to the substrate than the semiconductor layer.

Abstract: The active matrix substrate of the invention includes: a storage capacitor formed on a board; a first insulating layer formed on the storage capacitor; a semiconductor layer formed above the storage capacitor via the first insulating layer: a gate insulating layer formed on the semiconductor layer; a gate electrode layer including a gate electrode formed above the semiconductor layer via the gate insulating layer; a second insulating layer covering the gate electrode layer and the semiconductor layer; a first light-shielding layer formed above the semiconductor layer via the second insulating layer to cover at least a channel region of the semiconductor layer; a third insulating layer formed on the first light-shielding layer; a source electrode layer including source and drain electrodes formed on the third insulating layer; a fourth insulating layer formed on the source electrode layer; and a pixel electrode formed on the fourth insulating layer and electrically connected to the drain electrode.

Abstract: A thin-film transistor includes: a pair of n-type heavily doped regions that are horizontally spaced apart from each other; p-type channel regions that are located between the n-type heavily doped regions so as to face their associated gate electrodes, respectively; an n-type intermediate region provided between two adjacent ones of the channel regions; and two pairs of lightly doped regions. The lightly doped regions in one of the two pairs have mutually different carrier concentrations and are located between one of the heavily doped regions and one of the channel regions that is closer to the heavily doped region than any other channel region is. The lightly doped regions in the other pair also have mutually different carrier concentrations and are located between the other heavily doped region and another one of the channel regions that is closer to the heavily doped region than any other channel region is.