Patents by Inventor Tohru Ueda

Tohru Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11215891
    Abstract: An active matrix substrate includes: a substrate; lower bus lines and upper bus lines; a lower insulating layer positioned between the lower bus lines and the upper bus lines; an oxide semiconductor TFT that are disposed in each pixel region and have an oxide semiconductor layer disposed on the lower insulating layer; pixel electrodes disposed in each pixel region; and wiring connection units arranged in a non-display region. Each wiring connection unit includes: a lower conductive layer formed using the same conductive film as the lower bus lines; an insulating layer that extends on the lower conductive layer and includes the lower insulating layer. The lower bus lines and the lower conductive layer have a first laminated structure including a metal layer and a transparent conductive layer that covers an upper surface and a side surface of the metal layer.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: January 4, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hideki Kitagawa, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Tatsuya Kawasaki, Teruyuki Ueda, Hajime Imai, Tohru Daitoh
  • Patent number: 11205729
    Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle ?1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle ?2 between a side surface and a lower surface of the upper oxide semiconductor layer.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: December 21, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Teruyuki Ueda, Masamitsu Yamanaka, Tohru Daitoh, Hajime Imai, Kengo Hara
  • Publication number: 20170130768
    Abstract: A bearing raceway ring (25) disposed near a mounting section (9) is disposed on the outer periphery of a circular cylinder section (19). A fluid-sealed chamber (40) in which a measurement liquid is hermetically enclosed is provided between a first member (8) and the bearing raceway ring (25) which is disposed near the mounting section (9). Pressure acting on the fluid to be measured changes as the bearing raceway ring (25) moves in the cylinder-axis direction, the bearing raceway ring (25) being disposed near the mounting section (9). The fluid-sealed chamber (40) is provided with a pressure sensor (44) capable of detecting a change in the pressure of the fluid to be measured.
    Type: Application
    Filed: April 14, 2015
    Publication date: May 11, 2017
    Applicant: NSK LTD.
    Inventors: Yasuyuki MATSUDA, Tohru UEDA, Masafumi HIKIDA
  • Patent number: 9625332
    Abstract: In order to implement a structure capable of improving the resolution of torque measurement while preventing the plastic deformation of a torsion bar (15), an input-side stopper (61) having an uneven shape (gear shape) in the circumferential direction is provided in a portion of an input-side rotating body (55) that includes an input shaft (13) and an input gear (7), and an output-side stopper (63) having an uneven shape (gear shape) in the circumferential direction is provided in a portion of an output-side rotating body (56) that includes an output shaft (14) and an output gear (8). The input-side stopper (61) and the output-side stopper (63) are combined so as to be engaged to be able to transmit torque only when the torsional angle within the elastic range of the torsion bar (15) reaches a predetermined amount.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: April 18, 2017
    Assignee: NSK Ltd.
    Inventors: Tomoharu Saito, Yasuyuki Matsuda, Daisuke Gunji, Masafumi Hikida, Kazutaka Tanaka, Tohru Ueda, Yuka Kaneko, Tetsu Takehara, Hiroyasu Yoshioka
  • Publication number: 20160195442
    Abstract: In order to implement a structure capable of improving the resolution of torque measurement while preventing the plastic deformation of a torsion bar (15), an input-side stopper (61) having an uneven shape (gear shape) in the circumferential direction is provided in a portion of an input-side rotating body (55) that includes an input shaft (13) and an input gear (7), and an output-side stopper (63) having an uneven shape (gear shape) in the circumferential direction is provided in a portion of an output-side rotating body (56) that includes an output shaft (14) and an output gear (8). The input-side stopper (61) and the output-side stopper (63) are combined so as to be engaged to be able to transmit torque only when the torsional angle within the elastic range of the torsion bar (15) reaches a predetermined amount.
    Type: Application
    Filed: September 3, 2014
    Publication date: July 7, 2016
    Inventors: Tomoharu SAITO, Yasuyuki MATSUDA, Daisuke GUNJI, Masafumi HIKIDA, Kazutaka TANAKA, Tohru UEDA, Yuka KANEKO, Tetsu TAKEHARA, Hiroyasu YOSHIOKA
  • Patent number: 8593138
    Abstract: A bearing residual life prediction method, a bearing residual life diagnostic apparatus and a bearing diagnostic system can be provided. The bearing diagnostic system 20 includes: an eddy current tester 11 that measures the impedance X of a certain portion of a bearing 24 before and after the use of the bearing; a bearing information transmitter 30 that transmits bearing information s1 containing the impedance X; and a bearing information receiver 31 that receives the information; a diagnostic section 12 that obtains the residual life information s2 of the bearing 24 based on the received impedance X; and a life information transmitter 36 that transmits the residual life information s2; and a life information receiver 40 that receives the information. Hence, the bearing used by the user can be inspected nondestructively, and the residual life of the bearing can be predicted.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: November 26, 2013
    Assignee: NSK Ltd.
    Inventors: Tsuyoshi Nomura, Takamasa Ohira, Nobuaki Mitamura, Masahide Natori, Tohru Ueda, Ichiro Joko, Hidenobu Magami
  • Publication number: 20110241661
    Abstract: A bearing residual life prediction method, a bearing residual life diagnostic apparatus and a bearing diagnostic system can be provided. The bearing diagnostic system 20 includes: an eddy current tester 11 that measures the impedance X of a certain portion of a bearing 24 before and after the use of the bearing; a bearing information transmitter 30 that transmits bearing information s1 containing the impedance X; and a bearing information receiver 31 that receives the information; a diagnostic section 12 that obtains the residual life information s2 of the bearing 24 based on the received impedance X; and a life information transmitter 36 that transmits the residual life information s2; and a life information receiver 40 that receives the information. Hence, the bearing used by the user can be inspected nondestructively, and the residual life of the bearing can be predicted.
    Type: Application
    Filed: December 16, 2010
    Publication date: October 6, 2011
    Applicant: NSK LTD.
    Inventors: Tsuyoshi Nomura, Takamasa Ohira, Nobuaki Mitamura, Masahide Natori, Tohru Ueda, Ichiro Joko, Hidenobu Magami
  • Patent number: 7435007
    Abstract: A roughness of an outer ring raceway surface 14 formed on an inner peripheral surface of an outer ring 13 is made larger than a roughness of inner ring raceway surfaces 12a, 12b of an inner ring 11. Also, an average roughness Ra of the outer ring raceway surface 14 is set within 0.1 ?m?Ra?0.5 ?m in an axial direction and a circumferential direction in ranges of b1/(B/2)?0.9, b2/ (B/2)?0.9 and in a measured length of 0.1 mm to 1.0 mm where B is a width of the outer ring 13 and b1, b2 are a distance from both end surfaces of the outer ring 13 in the axial direction respectively. A roughness parameter S of the outer ring raceway surface is set within 0<S?20 ?m.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: October 14, 2008
    Assignee: NSK Ltd.
    Inventors: Kouji Ueda, Tohru Ueda
  • Publication number: 20070092174
    Abstract: A roughness of an outer ring raceway surface 14 formed on an inner peripheral surface of an outer ring 13 is made larger than a roughness of inner ring raceway surfaces 12a, 12b of an inner ring 11. Also, an average roughness Ra of the outer ring raceway surface 14 is set within 0.1 ?m?Ra?0.5 ?m in an axial direction and a circumferential direction in ranges of b1/(B/2)?0.9, b2/ (B/2)?0.9 and in a measured length of 0.1 mm to 1.0 mm where B is a width of the outer ring 13 and b1, b2 are a distance from both end surfaces of the outer ring 13 in the axial direction respectively. A roughness parameter S of the outer ring raceway surface is set within 0<S?20 ?m.
    Type: Application
    Filed: November 12, 2004
    Publication date: April 26, 2007
    Inventors: Kouji Ueda, Tohru Ueda
  • Patent number: 7129521
    Abstract: The problem is to provide a technology to reduce a light leakage current in order to obtain a good display. One kind or plurality kinds of elements chosen from argon, germanium, silicon, helium, neon, krypton, and xenon are implanted in a crystalline semiconductor layer, to distribute crystal defects due to the aforementioned element implantation by uniform and suitable density in the semiconductor film, making recombination centers of carriers, to thereby suppress alight sensitivity without spoiling a high degree of carrier movement included in a crystalline semiconductor layer.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: October 31, 2006
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hiroshi Shibata, Osamu Nakamura, Shunichi Naka, Tohru Ueda
  • Patent number: 7075594
    Abstract: A liquid crystal display device includes an active matrix substrate; a counter substrate; and a liquid crystal layer interposed between the active matrix substrate and the counter substrate. The active matrix substrate includes a plate; a thin film transistor provided on the plate; and a side light shielding layer for covering at least a portion of a side surface of the thin film transistor.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: July 11, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Kazuhiko Inoguchi, Yoshinori Higami
  • Publication number: 20050258421
    Abstract: The problem is to provide a technology to reduce a light leakage current in order to obtain a good display. One kind or plurality kinds of elements chosen from argon, germanium, silicon, helium, neon, krypton, and xenon are implanted in a crystalline semiconductor layer, to distribute crystal defects due to the aforementioned element implantation by uniform and suitable density in the semiconductor film, making recombination centers of carriers, to thereby suppress alight sensitivity without spoiling a high degree of carrier movement included in a crystalline semiconductor layer.
    Type: Application
    Filed: April 4, 2003
    Publication date: November 24, 2005
    Inventors: Hiroshi Shibata, Osamu Nakamura, Shunichi Naka, Tohru Ueda
  • Patent number: 6927809
    Abstract: The active matrix substrate of the invention includes: a storage capacitor formed on a board; a first insulating layer formed on the storage capacitor; a semiconductor layer formed above the storage capacitor via the first insulating layer: a gate insulating layer formed on the semiconductor layer; a gate electrode layer including a gate electrode formed above the semiconductor layer via the gate insulating layer; a second insulating layer covering the gate electrode layer and the semiconductor layer; a first light-shielding layer formed above the semiconductor layer via the second insulating layer to cover at least a channel region of the semiconductor layer; a third insulating layer formed on the first light-shielding layer; a source electrode layer including source and drain electrodes formed on the third insulating layer; a fourth insulating layer formed on the source electrode layer; and a pixel electrode formed on the fourth insulating layer and electrically connected to the drain electrode.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: August 9, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahito Gotoh, Tohru Ueda, Yoshinori Higami
  • Patent number: 6894754
    Abstract: The invention involves: the forming of a dummy pattern for planarization between convex portions (for example, between lead electrodes and a signal wire pattern) of irregularities caused by a patterned layer on a surface on which at least one interlayer insulating film is formed, so as to be separated by a predetermined distance from the convex portions; the forming of interlayer insulating films 7a-7d so as to fill up gaps between the dummy pattern and the convex portions; and the planarizing of a surface. Thereby, the invention is capable of relaxing requirements on uniformity in the thickness of the film to be polished and the thickness of the polished portion.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: May 17, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tohru Ueda
  • Publication number: 20050073620
    Abstract: An active matrix substrate of the present invention has a substrate, a thin-film transistor and a capacitive element provided on the principal plane of the substrate, and a scanning line for supplying a scanning signal to the thin-film transistor, in which the thin-film transistor has a semiconductor layer including a channel region and a gate electrode formed on the semiconductor layer. The capacitive element is located at a position opposite to the substrate at the both sides of the thin-film transistor. The scanning line is formed by a conductive layer different from the gate electrode and located at a position closer to the substrate than the semiconductor layer.
    Type: Application
    Filed: July 16, 2004
    Publication date: April 7, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masahito Gotoh, Tohru Ueda
  • Publication number: 20040257489
    Abstract: The active matrix substrate of the invention includes: a storage capacitor formed on a board; a first insulating layer formed on the storage capacitor; a semiconductor layer formed above the storage capacitor via the first insulating layer: a gate insulating layer formed on the semiconductor layer; a gate electrode layer including a gate electrode formed above the semiconductor layer via the gate insulating layer; a second insulating layer covering the gate electrode layer and the semiconductor layer; a first light-shielding layer formed above the semiconductor layer via the second insulating layer to cover at least a channel region of the semiconductor layer; a third insulating layer formed on the first light-shielding layer; a source electrode layer including source and drain electrodes formed on the third insulating layer; a fourth insulating layer formed on the source electrode layer; and a pixel electrode formed on the fourth insulating layer and electrically connected to the drain electrode.
    Type: Application
    Filed: October 27, 2003
    Publication date: December 23, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masahito Gotoh, Tohru Ueda, Yoshinori Higami
  • Patent number: 6828585
    Abstract: A thin-film transistor includes: a pair of n-type heavily doped regions that are horizontally spaced apart from each other; p-type channel regions that are located between the n-type heavily doped regions so as to face their associated gate electrodes, respectively; an n-type intermediate region provided between two adjacent ones of the channel regions; and two pairs of lightly doped regions. The lightly doped regions in one of the two pairs have mutually different carrier concentrations and are located between one of the heavily doped regions and one of the channel regions that is closer to the heavily doped region than any other channel region is. The lightly doped regions in the other pair also have mutually different carrier concentrations and are located between the other heavily doped region and another one of the channel regions that is closer to the heavily doped region than any other channel region is.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: December 7, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tohru Ueda
  • Patent number: 6714266
    Abstract: In a transmission type liquid crystal display device, a semiconductor thin film is formed for each pixel below a signal wiring, a gate wiring, an auxiliary capacitance wiring and a lead electrode which are made of a light shading material via an insulating film. A region that belongs to the semiconductor thin film and is located below the signal wiring and below the gate wiring is made to serve as a channel region of a TFT. Regions that belong to the semiconductor thin film and are located on both sides of the channel region below the signal wiring are made to serve as a source region and a drain region of the TFT, respectively. Further, a region that belongs to the semiconductor thin film and is located below the auxiliary capacitance wiring is made to serve as an auxiliary capacitance electrode region.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: March 30, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Yoshinori Higami
  • Publication number: 20040008295
    Abstract: A liquid crystal display device includes an active matrix substrate; a counter substrate; and a liquid crystal layer interposed between the active matrix substrate and the counter substrate. The active matrix substrate includes a plate; a thin film transistor provided on the plate; and a side light shielding layer for covering at least a portion of a side surface of the thin film transistor.
    Type: Application
    Filed: July 8, 2003
    Publication date: January 15, 2004
    Inventors: Tohru Ueda, Kazuhiko Inoguchi, Yoshinori Higami
  • Patent number: 6639245
    Abstract: An a-Si film 12 is formed on the whole surface of a quartz substrate 11, and a protection film 13 is formed in a region to be used as a display unit on the a-Si film 12. Subsequently, after a catalyst metal is selectively introduced into the whole surface of a region to be used as a peripheral drive circuit on the a-Si film 12, crystal growth is allowed by heating the a-Si film 12 to form a CG silicon film 14 and a p-Si film 15. Then, the catalyst metal in the CG silicon film 14 and the p-Si film 15 is removed by gettering. The concentration of the catalyst metal in the CG silicon film 14 is in the range of 1×1013 atoms/cm13 or higher and lower than 1×1015 atoms/cm3. The concentration of the catalyst metal in the p-Si film for a display unit 15 is made lower than the concentration of the catalyst metal in the CG silicon film 14b for a peripheral drive circuit.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: October 28, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahito Gotoh, Tohru Ueda