Patents by Inventor Tohru Ueda

Tohru Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6714266
    Abstract: In a transmission type liquid crystal display device, a semiconductor thin film is formed for each pixel below a signal wiring, a gate wiring, an auxiliary capacitance wiring and a lead electrode which are made of a light shading material via an insulating film. A region that belongs to the semiconductor thin film and is located below the signal wiring and below the gate wiring is made to serve as a channel region of a TFT. Regions that belong to the semiconductor thin film and are located on both sides of the channel region below the signal wiring are made to serve as a source region and a drain region of the TFT, respectively. Further, a region that belongs to the semiconductor thin film and is located below the auxiliary capacitance wiring is made to serve as an auxiliary capacitance electrode region.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: March 30, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Yoshinori Higami
  • Publication number: 20040008295
    Abstract: A liquid crystal display device includes an active matrix substrate; a counter substrate; and a liquid crystal layer interposed between the active matrix substrate and the counter substrate. The active matrix substrate includes a plate; a thin film transistor provided on the plate; and a side light shielding layer for covering at least a portion of a side surface of the thin film transistor.
    Type: Application
    Filed: July 8, 2003
    Publication date: January 15, 2004
    Inventors: Tohru Ueda, Kazuhiko Inoguchi, Yoshinori Higami
  • Patent number: 6639245
    Abstract: An a-Si film 12 is formed on the whole surface of a quartz substrate 11, and a protection film 13 is formed in a region to be used as a display unit on the a-Si film 12. Subsequently, after a catalyst metal is selectively introduced into the whole surface of a region to be used as a peripheral drive circuit on the a-Si film 12, crystal growth is allowed by heating the a-Si film 12 to form a CG silicon film 14 and a p-Si film 15. Then, the catalyst metal in the CG silicon film 14 and the p-Si film 15 is removed by gettering. The concentration of the catalyst metal in the CG silicon film 14 is in the range of 1×1013 atoms/cm13 or higher and lower than 1×1015 atoms/cm3. The concentration of the catalyst metal in the p-Si film for a display unit 15 is made lower than the concentration of the catalyst metal in the CG silicon film 14b for a peripheral drive circuit.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: October 28, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahito Gotoh, Tohru Ueda
  • Publication number: 20030184697
    Abstract: The invention involves: the forming of a dummy pattern for planarization between convex portions (for example, between lead electrodes and a signal wire pattern) of irregularities caused by a patterned layer on a surface on which at least one interlayer insulating film is formed, so as to be separated by a predetermined distance from the convex portions; the forming of interlayer insulating films 7a-7d so as to fill up gaps between the dummy pattern and the convex portions; and the planarizing of a surface. Thereby, the invention is capable of relaxing requirements on uniformity in the thickness of the film to be polished and the thickness of the polished portion.
    Type: Application
    Filed: February 24, 2003
    Publication date: October 2, 2003
    Inventor: Tohru Ueda
  • Patent number: 6493046
    Abstract: A liquid crystal display device provided with an insulating substrate, a thin film transistor formed on the insulating substrate, and a pixel electrode and a storage capacitor electrically connected to the thin film transistor, includes a first conductive layer formed on the insulating substrate; a first insulating layer formed on the first conductive layer and having an opening for exposing a part of the first conductive layer; a second conductive layer formed on the first conductive layer at least within the opening; a second insulating layer for covering the second conductive layer; and a third conductive layer for covering the second insulating layer at least within the opening, and the storage capacitor is formed from a stacked layer structure including the second conductive layer, the second insulating layer and the third conductive layer.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: December 10, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tohru Ueda
  • Publication number: 20020149017
    Abstract: An a-Si film 12 is formed on the whole surface of a quartz substrate 11, and a protection film 13 is formed in a region to be used as a display unit on the a-Si film 12. Subsequently, after a catalyst metal is selectively introduced into the whole surface of a region to be used as a peripheral drive circuit on the a-Si film 12, crystal growth is allowed by heating the a-Si film 12 to form a CG silicon film 14 and a p-Si film 15. Then, the catalyst metal in the CG silicon film 14 and the p-Si film 15 is removed by gettering. The concentration of the catalyst metal in the CG silicon film 14 is in the range of 1×1013 atoms/cm3 or higher and lower than 1×1015 atoms/cm3. The concentration of the catalyst metal in the p-Si film for a display unit 15 is made lower than the concentration of the catalyst metal in the CG silicon film 14b for a peripheral drive circuit.
    Type: Application
    Filed: April 11, 2002
    Publication date: October 17, 2002
    Inventors: Masahito Gotoh, Tohru Ueda
  • Publication number: 20020125535
    Abstract: A thin-film transistor includes: a pair of n-type heavily doped regions that are horizontally spaced apart from each other; p-type channel regions that are located between the n-type heavily doped regions so as to face their associated gate electrodes, respectively; an n-type intermediate region provided between two adjacent ones of the channel regions; and two pairs of lightly doped regions. The lightly doped regions in one of the two pairs have mutually different carrier concentrations and are located between one of the heavily doped regions and one of the channel regions that is closer to the heavily doped region than any other channel region is. The lightly doped regions in the other pair also have mutually different carrier concentrations and are located between the other heavily doped region and another one of the channel regions that is closer to the heavily doped region than any other channel region is.
    Type: Application
    Filed: December 18, 2001
    Publication date: September 12, 2002
    Inventor: Tohru Ueda
  • Patent number: 6346436
    Abstract: A nanometer-size quantum thin line is formed on a semiconductor substrate of a Si substrate or the like by means of the general film forming technique, lithographic technique and etching technique. By opportunely using the conventional film forming technique, photolithographic technique and etching technique, a second oxide film that extends in the perpendicular direction is formed on an Si substrate. Then, by removing the second oxide film that extends in the perpendicular direction, a second nitride film located below the film and a first oxide film located below the film by etching, a groove for exposing the Si substrate is formed. Then, a Si thin line is made to epitaxially grow on the exposed portion of the Si substrate. The quantum thin line is thus formed without using any special fine processing technique. The width of the groove can be accurately controlled in nanometers by controlling the film thickness of the second oxide film that is formed by oxidizing the surface of the second nitride film.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: February 12, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasumori Fukushima, Tohru Ueda, Kunio Kamimura
  • Patent number: 6337259
    Abstract: An amorphous silicon film is deposited on a quartz substrate, and a metal of Ni is introduced into the amorphous silicon film so that the amorphous silicon film is crystallized. Phosphorus is ion-implanted with an oxide pattern used as a mask. A heating process is performed in a nitrogen atmosphere, by which Ni is gettered. A heating process is performed in an O2 atmosphere, by which Ni is gettered into the oxide. Like this, by performing the first gettering in a non-oxidative atmosphere, the Ni concentration can be reduced to such a level that oxidation does not cause any increase of irregularities or occurrence of pinholes. Thus, in a second gettering, enough oxidation can be effected without minding any increase of irregularities and occurrence of pinholes, so that the Ni concentration can be reduced to an extremely low level. Also, a high-quality crystalline silicon film free from surface irregularities and pinholes can be obtained.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: January 8, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Yasumori Fukushima, Yoshinori Higami
  • Patent number: 6326311
    Abstract: There is provided a microstructure producing method capable of achieving satisfactory uniformity and reproducibility of the growth position, size and density of a minute particle or thin line and materializing a semiconductor device which can reduce the cost through simple processes without using any special microfabrication technique and has superior characteristics appropriate for mass-production with high yield and high productivity as well as a semiconductor device employing the microstructure. An oxide film 12 having a region 12a of a great film thickness and a region 12b of a small film thickness are formed on the surface of a semiconductor substrate 11. Next, a microstructure that is a thin line 15 made of silicon Si is selectively formed only on the surface of the small-film-thickness region 12b of the oxide film 12.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: December 4, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Yasumori Fukushima, Fumitoshi Yasuo
  • Patent number: 6310376
    Abstract: There is provided is a semiconductor storage device that can reduce a dispersion in characteristics such as a threshold voltage and a writing performance and has a low consumption power and a non-volatility. There are included a source region 9 and a drain region 10 formed on a silicon substrate 1, a channel region 3a located between the source and drain regions 9 and 10, a gate electrode 8 that is formed above the channel region 3a and controls a channel current flowing through the channel region 3a, and a control gate insulating film 7, a floating gate 6 and a tunnel insulating film 4 that are arranged in order from the gate electrode 8 side between the channel region 3a and the gate electrode 8. The floating gate 6 is comprised of a plurality of crystal grains 6a linearly discretely arranged substantially parallel to the surface of the channel region 3a.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: October 30, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Kenta Nakamura, Yasumori Fukushima
  • Patent number: 6103600
    Abstract: A quantum dot and quantum fine wire forming method is provided which can allow control of the position for crystalline particle growth and enables formation of particles with high uniformity in size and density and with high reproducibility. After an Si substrate is formed with a step by a dry etching method, an SiO.sub.2 film is formed on the surface of the substrate. The interior of a reaction chamber is evacuated to a vacuum of 10.sup.-8 Torr, and then an Si.sub.2 H.sub.6 gas is introduced into the reaction chamber to flow therein so that Si crystal particles (quantum dots) are formed along the step. The step is formed by conventional photolithography and dry etching; therefore, the position for quantum dot growth can be easily controlled. By controlling the rate and time period of gas flow and the temperature of the substrate it is possible to form quantum fine wires, and to control the size of quantum dots and/or thickness of quantum fine wires.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: August 15, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Yasumori Fukushima, Kenta Nakamura
  • Patent number: 6090666
    Abstract: There are provided a method for fabricating semiconductor nanocrystals which are highly controllable and less variable in density and size, as well as a semiconductor memory device which, with the use of the semiconductor nanocrystals, allows thickness of a insulating film between nanocrystals and channel region to be easily controlled and involves less variations in characteristics such as threshold and programming performance, and which is fast reprogrammable and has nonvolatility. Under a low pressure below atmospheric pressure, an amorphous silicon thin film 3 is deposited on a tunnel insulating film 2 formed on a silicon substrate 1.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: July 18, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Kenta Nakamura, Yasumori Fukushima
  • Patent number: 6013922
    Abstract: A semiconductor storage element has a source region, a drain region, and a channel region connecting the source region with the drain region, which each are formed on an insulation film of a substrate. A gate insulation film is formed between the channel region and a gate electrode. The source region, the drain region, and the channel region consist of an aggregate of spherical grains which are arranged two-dimensionally on the insulation film and connected with one another such that the adjacent spherical grains are conductive to one another. The channel region contains at least one carrier trap region provided at a location other than an electric path thereof.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: January 11, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Kenta Nakamura, Yasumori Fukushima
  • Patent number: 5705630
    Abstract: 2'-Methylidenepyrimidine nucleoside compounds of the general formula: ##STR1## wherein R.sup.1 stands for amino or hydroxy group; R.sup.2 stands for a halogen or a lower alkyl when R.sup.1 is amino or R.sup.2 stands for an alkyl having 2 to 4 carbon atoms, an alkynyl having 2 to 4 carbon atoms or a haloalkyl when R.sup.1 is hydroxy group; and R.sup.3 stands for hydrogen or a phosphoric acid residue, or salts thereof, anticancer compositions containing one or more of these compounds and methods for production of these compounds.Said compounds and salts thereof exhibit noticeable antitumor activities and are useful as anticancer agents.
    Type: Grant
    Filed: January 7, 1992
    Date of Patent: January 6, 1998
    Assignees: Yoshitomi Pharmaceutical Industries, Ltd., Yamasa Shoyu Co., Ltd.
    Inventors: Tohru Ueda, Takuma Sasaki, Akira Matsuda, Keiji Yamagami, Akihiro Fujii
  • Patent number: 5654420
    Abstract: A process for preparing a compound of the formula: ##STR1## wherein R.sup.1 is a hydroxyl or an amino which may optionally be substituted; R.sup.2 is a hydrogen or a C.sub.1 -C.sub.4 alkyl; and R.sup.4a and R.sup.5a together represent a group of the formula: --R.sup.6 R.sup.7 Si--O--SiR.sup.6' R.sup.7', wherein R.sup.6, R.sup.7, R.sup.6' and R.sup.7' are the same or different and each is a C.sub.1 -C.sub.4 alkyl, which process comprises reacting a reducing agent and a cyanolating agent with a compound of the formula: ##STR2## wherein R.sup.9 is an alkoxythiocarbonyl having a C.sub.1 -C.sub.4 alkyl or an arylthiocarbonyl having a C.sub.6 -C.sub.10 aryl.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: August 5, 1997
    Assignee: Sankyo Company, Limited
    Inventors: Akira Matsuda, Tohru Ueda, deceased
  • Patent number: 5616567
    Abstract: The pyrimidine compounds of the present invention are represented by the following formula: ##STR1## and pharmaceutically acceptable salts thereof, wherein, R.sup.1 represents a hydroxyl or an amino which may be substituted by an acyl group; R.sup.2 represents a hydrogen atom or an alkyl having 1 to 4 carbons; R.sup.3 represents a hydrogen or a hydroxyl; and R.sup.4 and R.sup.5 each represent a hydrogen or together form a group --R.sup.6 R.sup.7 Si--O--SiR.sup.6' R.sup.7' --, wherein R.sup.6, R.sup.7, R.sup.6' and R.sup.7' are the same or different from one another and each represent an alkyl having 1 to 4 carbons. The compounds of the present invention exhibit an excellent antitumor effect.
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: April 1, 1997
    Assignee: Sankyo Company, Limited
    Inventors: Takuma Sasaki, Akira Matsuda, Tohru Ueda, deceased
  • Patent number: 5459254
    Abstract: The present invention relates to a novel compound represented by the following formula [I] which is useful as a synthetic intermediate of a 2-alkynyladenosine.The present invention also relates to a process for producing the compound and a process for producing a 2-alkynyladenosine [IV] by way of the compound.Further, the present invention relates to a 2-alkynyladenosine derivative represented by the following formula [V] having excellent storage stability and, to a method of storing the 2-alkynyladenosine in the form of that derivative. ##STR1## [I] A=a leaving group, [II] A=NH.sub.2,[V] A=NHR.sup.4,wherein R.sup.1 through R.sup.4 represent a hydrogen atom or a protective group, and n denotes an integer of 1 to 15, provided that R.sup.1 through R.sup.4 do not represent a hydrogen atom simultaneously.
    Type: Grant
    Filed: November 10, 1993
    Date of Patent: October 17, 1995
    Assignees: Yamasa Shoyu Kabushiki Kaisha, Toa Eiyo Ltd.
    Inventors: Toyofumi Yamaguchi, Takanori Miyashita, Shinji Sakata, Toichi Abiru, Akira Matsuda, Tohru Ueda, Kentaro Kogi
  • Patent number: 5430139
    Abstract: Disclosed are novel 2'-alkylidenepyrimidine nucleoside derivatives represented by formula [I]: ##STR1## R.sup.1 is an amino group or a hydroxy group, R.sup.2 is a hydrogen atom, a halogen atom or a lower alkyl group, R.sup.3 is a hydrogen atom or a lower alkyl group, and R.sup.4 is a hydrogen atom or a phosphate residue, or salts thereof. These novel compounds can be produced from uridine or cytidine derivatives by alkylidenating the 2'-position in the sugar moiety thereof with Wittig's reagent. Furthermore, the compounds have remarkable antiviral activities and therefore can provide novel antiviral agents.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: July 4, 1995
    Assignee: Yamasa Shoyu Kabushiki Kaisha
    Inventors: Akira Matsuda, Tohru Ueda, Kenji Takenuki, Haruhiko Machida
  • Patent number: 5401726
    Abstract: 2'-Methylidenepyrimidine nucleoside compounds of the general formula: ##STR1## wherein R.sup.1 stands for amino or hydroxy group; R.sup.2 stands for a halogen or a lower alkyl when R.sup.1 is amino or R.sup.2 stands for an alkyl having 2 to 4 carbon atoms, an alkynyl having 2 to 4 carbon atoms or a haloalkyl when R.sup.1 is hydroxy group; and R.sup.3 stands for hydrogen or a phosphoric acid residue, or salts thereof, compositions containing one or more of these compounds and methods for production of these compounds are disclosed.Said compounds and salts thereof exhibit noticeable antitumor activities.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: March 28, 1995
    Assignees: Yoshitomi Pharaceutical Industries, Ltd., Yamasa Shoyu Co., Ltd.
    Inventors: Tohru Ueda, Takuma Sasaki, Akira Matsuda, Keiji Yamagami, Akihiro Fujii