Patents by Inventor Tohru Yoshida

Tohru Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030131909
    Abstract: The present invention provides a steel pipe excellent in formability during hydraulic forming and the like and a method to produce the same, and more specifically: a steel pipe excellent in formability having an r-value of 1.4 or larger in the axial direction of the steel pipe, and the property that the average of the ratios of the X-ray intensity in the orientation component group of {110}<110> to {332}<110> on the plane at the center of the steel pipe wall thickness to the random X-ray intensity is 3.5 or larger, and/or the ratio of the X-ray intensity in the orientation component of {110}<110> on the plane at the center of the steel pipe wall thickness to the random X-ray intensity is 5.
    Type: Application
    Filed: February 6, 2002
    Publication date: July 17, 2003
    Inventors: Naoki Yoshinaga, Nobuhiro Fujita, Manabu Takashi, Yasuhiro Shinohara, Tohru Yoshida, Natsuko Sugiura
  • Patent number: 6375765
    Abstract: A thin ferritic steel sheet having an excellent shape fixability capable of being used for bending is provided, comprising: at least 0.027 to less than 0.05 mass % of C, 0.01 to 1.0 mass % of Si, 0.01 to 2.0 mass % of Mn, not more than 0.15 mass % of P, not more than 0.03 mass % of S, 0.01 to 0.1 mass % of Al, not more than 0.01 mass % of N, not more than 0.007 mass % of O, the balance being Fe and inevitable impurities, wherein a ratio of presence of {100} planes parallel with a face of the steel sheet to {111} planes is not less than 1.0, and TS×El, which represents a product of maximum tensile strength (TS) multiplied by rupture elongation (El) of the steel sheet, is at least 13,860 MPA %.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: April 23, 2002
    Assignee: Nippon Steel Corporation
    Inventors: Manabu Takahashi, Osamu Akisue, Koji Kishida, Matsuo Usuda, Tohru Yoshida
  • Publication number: 20010050887
    Abstract: An optical disc recording device controls a rotational rate of an optical disc and an optical disc recording device recording using a constant angular velocity method, thereby efficiently using the performance of the optical disc. A CPU reads management information (a maximum address value) for a farthest recording region, which is located at a circumference farthest from a center of the optical disc. A distance from the center of the optical disc to the farthest circumference of the recording region is calculated based on the read maximum address value. The rotational rate is calculated based on the calculated distance so that the recorded data rate of the farthest recording region is a maximum recorded data rate for the optical disc, and therefore is set to be used by a servo controller.
    Type: Application
    Filed: January 16, 2001
    Publication date: December 13, 2001
    Inventor: Tohru Yoshida
  • Publication number: 20010043527
    Abstract: A device that records information on an optical disc and a method for recording the information on the optical disc, so as to maintain a constant recording quality when the information is recorded on the optical disc using a constant number of the rotations to control the speed. The recording device includes a linear velocity detector detects a linear velocity which is a velocity of a spot of a light, which is irradiated to record the information on a surface of the optical disc, in a tangential direction of a circumference of the optical disc, and an optical power controller controlling the optical power of the light to record the information on the surface of the optical disc based on the linear velocity detected by the linear velocity detector.
    Type: Application
    Filed: March 16, 2001
    Publication date: November 22, 2001
    Inventor: Tohru Yoshida
  • Patent number: 6011292
    Abstract: A semiconductor device with an alignment mark has a first well of a first conductivity type formed on the entire surface of a semiconductor substrate, a second well of a second conductivity type opposite to the first conductivity type formed within a desired region of the first well, and an oxide film formed on said first well and said second well, the first well having a higher impurity concentration than that of the semiconductor substrate, the depth of the first well being greater than that of said second well, and the oxide film having a step-wise alignment mark at a boundary between the first well and the second well.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: January 4, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tohru Yoshida
  • Patent number: 5460984
    Abstract: A method of manufacturing a semiconductor device including the steps of: forming an oxide film on the surface of a semiconductor substrate, and thereafter injecting ions of a first conductivity type on the entire surface of the semiconductor substrate; forming a first well through a first thermal diffusion; injecting ions of a second conductivity type through the oxide film into a second well region within the first well; and removing the oxide film formed on the second well region, and thereafter forming a second well having a depth smaller than that of the first well. The semiconductor device manufactured by this method has a first well of a first conductivity type formed on the entire surface of a semiconductor substrate and having higher impurity concentration than that of the semiconductor substrate and a second well of a second conductivity type opposite to said first conductivity type formed within a desired region of said first well.
    Type: Grant
    Filed: September 10, 1990
    Date of Patent: October 24, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tohru Yoshida
  • Patent number: 5387265
    Abstract: In the semiconductor manufacturing apparatus according to the present invention, there are provided a cassette stocker for accommodating wafer cassettes loaded with wafers, a reaction furnace provided with heating means, a reaction gas introducing means for introducing reaction gas into the reaction furnace, a gas discharging means for discharging exhaust gas in the reaction furnace, a boat for supporting wafers, a buffer cassette stocker for storing unprocessed wafers, a boat elevating means for inserting the boat into and retrieving the boat from the reaction furnace, a wafer transfer means for transferring wafers between the boat and the wafer cassette accommodated on the cassette stocker, and a wafer cassette transfer means for transferring wafer cassettes between the buffer cassette stocker and the cassette stocker, and the buffer cassette stocker is enclosed to provide an antioxidation area to prevent natural oxidation of the wafers in standby status.
    Type: Grant
    Filed: October 26, 1992
    Date of Patent: February 7, 1995
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Satoshi Kakizaki, Toshikazu Karino, Shoichiro Izumi, Mikio Koizumi, Makoto Ozawa, Fumihide Ikeda, Tohru Yoshida, Ryoji Saito
  • Patent number: 5334875
    Abstract: There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: August 2, 1994
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd.
    Inventors: Toshio Sugano, Kohji Nagaoka, Seiichiro Tsukui, Yoshiaki Wakashima, Michio Tanimoto, Masayuki Watanabe, Suguru Sakaguchi, Kunihiko Nishi, Aizo Kaneda, Kohji Serizawa, Michiharu Honda, Tohru Yoshida, Takeshi Komaru, Atsushi Nakamura
  • Patent number: 5278090
    Abstract: A semiconductor region of a first conductivity type is formed in a column configuration on a semiconductor substrate, and acts as a source region (or a drain region) and a storage node electrode. A second semiconductor region of the first conductivity type is formed with a capacitor insulation film disposed between it and the side wall of the first semiconductor region and acts as a cell plate electrode. A third semiconductor region of a second conductivity type which is formed in an annular configuration is formed on the upper portion of the first semiconductor region and acts as a channel region. A first conductive layer is formed with a gate insulation film disposed between the first conductive layer and each of the inner and outer side walls of the third semiconductor region and acts as a transfer gate electrode.
    Type: Grant
    Filed: September 9, 1992
    Date of Patent: January 11, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tohru Yoshida
  • Patent number: 5198888
    Abstract: There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: March 30, 1993
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd.
    Inventors: Toshio Sugano, Kohji Nagaoka, Seiichiro Tsukui, Yoshiaki Wakashima, Michio Tanimoto, Masayuki Watanabe, Suguru Sakaguchi, Kunihiko Nishi, Aizo Kaneda, Kohji Serizawa, Michiharu Honda, Tohru Yoshida, Takeshi Komaru, Atsushi Nakamura
  • Patent number: 5191397
    Abstract: According to this invention, an SOI semiconductor device having a thin semiconductor film (15) formed on an insulating film (12) includes a semiconductor substrate (11), the insulating film (12) having a recess portion (13a, 13b) and formed on the semiconductor substrate (11), and a conductor (14a, 14b) buried in the recess portion (13a, 13b). In addition, the SOI semiconductor device further includes the semiconductor film (15) formed on the insulating film (12), and an impurity region (16) formed in the semiconductor film (15) and electrically connected to the conductor (14a, 14b).
    Type: Grant
    Filed: April 24, 1991
    Date of Patent: March 2, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tohru Yoshida
  • Patent number: 5166762
    Abstract: A semiconductor region of a first conductivity type is formed in a column configuration on a semiconductor substrate, and acts as a source region (or a drain region) and a storage node electrode. A second semiconductor region of the first conductivity type is formed with a capacitor insulation film disposed between it and the side wall of the first semiconductor region and acts as a cell plate electrode. A third semiconductor region of a second conductivity type which is formed in an annular configuration is formed on the upper portion of the first semiconductor region and acts as a channel region. A first conductive layer is formed with a gate insulation film disposed between the first conductive layer and each of the inner and outer side walls of the third semiconductor region and acts as a transfer gate electrode.
    Type: Grant
    Filed: January 10, 1991
    Date of Patent: November 24, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tohru Yoshida
  • Patent number: 5049956
    Abstract: In a memory call of an EPROM, a drain region, a channel region, and a source region are formed in a direction perpendicular to the surface of a semiconductor substrate. A trench is provided, which penetrates the drain region and the channel region and reaches the source region. A floating gate and a control gate are formed in the trench, in a direction perpendicular to the surface of the semiconductor substrate.
    Type: Grant
    Filed: July 6, 1990
    Date of Patent: September 17, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tohru Yoshida, Mitsumasa Furukawa
  • Patent number: 5028986
    Abstract: There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.
    Type: Grant
    Filed: December 23, 1988
    Date of Patent: July 2, 1991
    Assignees: Hitachi, Ltd., HitachiTobu Semiconductor, Ltd.
    Inventors: Toshio Sugano, Kohji Nagaoka, Seiichiro Tsukui, Yoshiaki Wakashima, Michio Tanimoto, Masayuki Watanabe, Suguru Sakaguchi, Kunihiko Nishi, Aizo Kaneda, Kohji Serizawa, Michiharu Honda, Tohru Yoshida, Takeshi Komaru, Atsushi Nakamura
  • Patent number: 4974658
    Abstract: Disclosed herein is a sheet shutter which is a shutter of the type in which a sheet-form shielding material is lifted and lowered to be used as a partition of the entrance or passage of factory, warehouse or the like. The sheet shutter comprises (a) a pair of sheet guides erected parallel with a predetermined spacing therebetween, each sheet guide having an uppr end; (b) a sheet case provided between the upper ends of the sheet guides; (c) a take-up drum rotatably supported within the sheet case, the take-up drum having an interior space; (d) a flexible sheet having a top edge and both of side edges, the both side edges being guided by the sheet guides in such a manner that the flexible sheet is lifted and lowered, and the top edges being attached to the take-up drum; and (e) a motor for rotationally driving the take-up drum, and motor being fixed to the sheet case and accommodated in the interior space of the take-up drum.
    Type: Grant
    Filed: February 22, 1989
    Date of Patent: December 4, 1990
    Assignee: Komatsu Denki Sangyo Kabushiki Kaisha
    Inventors: Akio Komatsu, Nakayoshi Imada, Shuichi Katsura, Tohru Yoshida
  • Patent number: 4833598
    Abstract: In a multiprocessor system in which a plurality of instruction processors (IP's) share a main storage (MS) and a channel controller (CHC) through a system controller (SC), when an I/O interrupt request is issued, IP's connected to the SC are examined to determine whether each of the IP's is executing an instruction which permits acceptance of the I/O interrupt request during the execution of the instruction. If one of the IP's is not executing such an instruction and can accept the I/O interrupt request, that IP will be selected.
    Type: Grant
    Filed: July 21, 1987
    Date of Patent: May 23, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Jiro Imamura, Katsuro Wakai, Tohru Yoshida