Abstract: Fixed pattern noise (FPN) reduction techniques in image sensors operated with pulse illumination are disclosed herein. In one embodiment, a method includes, during a first sub-exposure period of a frame, (a) operating a first tap of a pixel to capture a first signal corresponding to first charge at a first floating diffusion, the first charge corresponding to first light incident on a photosensor, and (b) operating a second tap of the pixel to capture a first parasitic signal corresponding to FPN at a second floating diffusion. The method further includes, during a second sub-exposure period of the frame, (a) operating the second tap to capture a second signal corresponding to second charge at the second floating diffusion, the second charge corresponding to second light incident on the photosensor, and (b) operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion.

Abstract: Fixed pattern noise (FPN) reduction techniques in image sensors operated with pulse illumination are disclosed herein. In one embodiment, a method includes, during a first sub-exposure period of a frame, (a) operating a first tap of a pixel to capture a first signal corresponding to first charge at a first floating diffusion, the first charge corresponding to first light incident on a photosensor, and (b) operating a second tap of the pixel to capture a first parasitic signal corresponding to FPN at a second floating diffusion. The method further includes, during a second sub-exposure period of the frame, (a) operating the second tap to capture a second signal corresponding to second charge at the second floating diffusion, the second charge corresponding to second light incident on the photosensor, and (b) operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.

Abstract: A time-of-flight (TOF) sensing system may include an illumination module and a sensor module. The sensor module may include an array of sensor pixels, pixel-level readout circuitry, and column-level readout circuitry coupled to the pixel-level readout circuitry via corresponding column lines. Pixel-level readout circuitry may be provided on a per-pixel basis (e.g., dedicated or unshared per-pixel readout circuitry may be provided for each pixel). Pixel-level readout circuitry may include one or more correlated double sampling stages and a storage stage. The storage stage may include a set of capacitors each configured to store different phase data generated by a corresponding pixel for a TOF sensing operation.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel in the array may be a global shutter pixel having a first charge storage node configured to capture scenery information and a second charge storage node configured to capture background information generated as a result of parasitic light and dark noise signals. The first and/or second charge storage nodes may each be provided with an overflow charge storage to provide high dynamic range (HDR) functionality. The background information may be subtracted from the scenery information to cancel out the desired background signal contribution and to obtain an HDR signal with high global shutter efficiency. The charge storage nodes may be implemented as storage diode or storage gate devices. The pixels may be backside illuminated pixels with optical diffracting structures and multiple microlenses formed at the backside to distribute light equally between the two charge storage nodes.

Abstract: A time-of-flight (TOF) sensing system may include an illumination module and a sensor module. The sensor module may include an array of sensor pixels, pixel-level readout circuitry, and column-level readout circuitry coupled to the pixel-level readout circuitry via corresponding column lines. Pixel-level readout circuitry may be provided on a per-pixel basis (e.g., dedicated or unshared per-pixel readout circuitry may be provided for each pixel). Pixel-level readout circuitry may include one or more correlated double sampling stages and a storage stage. The storage stage may include a set of capacitors each configured to store different phase data generated by a corresponding pixel for a TOF sensing operation.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to row control circuitry and column readout circuitry. An image pixel in the array may include a charge integration portion having a photodiode, a floating diffusion region, and a capacitor coupled to the floating diffusion region and may include a voltage-domain sampling portion having three capacitors. High light and low light image level and reset level signals may be sampled and stored at the voltage-domain sampling portion before being readout to the column readout circuitry during a readout operation. The high light reset level signal may be sampled and stored during the readout operation.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.

Abstract: Implementations of a semiconductor device may include a photodiode included in a second epitaxial layer of a semiconductor substrate; light shield coupled over the photodiode; and a first epitaxial layer located in one or more openings in the light shield. The first epitaxial layer and the second epitaxial layer may form a single crystal.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel in the array may be a global shutter pixel having a first charge storage node configured to capture scenery information and a second charge storage node configured to capture background information generated as a result of parasitic light and dark noise signals. The first and/or second charge storage nodes may each be provided with an overflow charge storage to provide high dynamic range (HDR) functionality. The background information may be subtracted from the scenery information to cancel out the desired background signal contribution and to obtain an HDR signal with high global shutter efficiency. The charge storage nodes may be implemented as storage diode or storage gate devices. The pixels may be backside illuminated pixels with optical diffracting structures and multiple microlenses formed at the backside to distribute light equally between the two charge storage nodes.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel in the array may be a global shutter pixel having a first charge storage node configured to capture scenery information and a second charge storage node configured to capture background information generated as a result of parasitic light and dark noise signals. The first and/or second charge storage nodes may each be provided with an overflow charge storage to provide high dynamic range (HDR) functionality. The background information may be subtracted from the scenery information to cancel out the desired background signal contribution and to obtain an HDR signal with high global shutter efficiency. The charge storage nodes may be implemented as storage diode or storage gate devices. The pixels may be backside illuminated pixels with optical diffracting structures and multiple microlenses formed at the backside to distribute light equally between the two charge storage nodes.

Abstract: An imaging system may include an image sensor having an image sensor. The image sensor may include an image sensor pixel array coupled to row control circuitry and column readout circuitry. The image sensor pixel array may include a plurality of image sensor pixels. Each image sensor pixel may include a photosensitive element configured to generate charge in response to incident light, a first charge storage structure configured to accumulate an overflow portion of the generated charge for a low gain signal and a second charge storage structure configured to store a remaining portion of the generated charge for a high gain signal. Each image sensor pixel may also include a dedicated overflow charge storage structure interposed between the first charge storage structure and a floating diffusion region.

Abstract: A time-of-flight (TOF) sensing system may include an illumination module and a sensor module. The sensor module may include an array of sensor pixels, pixel-level readout circuitry, and column-level readout circuitry coupled to the pixel-level readout circuitry via corresponding column lines. Pixel-level readout circuitry may be provided on a per-pixel basis (e.g., dedicated or unshared per-pixel readout circuitry may be provided for each pixel). Pixel-level readout circuitry may include one or more correlated double sampling stages and a storage stage. The storage stage may include a set of capacitors each configured to store different phase data generated by a corresponding pixel for a TOF sensing operation.

Abstract: An image sensor may include a pixel array coupled to column readout circuitry. The pixel array may be split into multiple sub-arrays. Readout circuitry may be shared between multiple columns in each sub-array or in the pixel array. The readout circuitry may be coupled to at least first and second pixels in first and second different columns. The readout circuitry may include amplifier circuitry that receives signals from both the first and second pixels. Two input capacitors for the amplifier circuitry may form two corresponding memory circuits, for the first and second columns, respectively. Two feedback capacitors for the amplifier circuitry may form two corresponding memory circuits, for the first and second columns, respectively. The readout circuitry may be configured to perform a shared reset level readout operation for the first and second pixels and to perform separate correlated double sampling readout operations for the first and second pixels.

Abstract: Image sensors may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates. A first n-epitaxial layer may be formed on a residual substrate; a first p-epitaxial layer may be formed on the first n-epitaxial layer; a second n-epitaxial layer may be formed on the first p-epitaxial layer; a second p-epitaxial layer may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates may be a deep trench that is filled with doped conductive material, lined with gate dielectric liner, and surrounded by a p-doped region. Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.

Abstract: An image sensor may include an array of image pixels. Control circuitry coupled to the array of pixels may be configured to operate the image pixels in an overflow mode of operation, in which each pixel generates an overflow image signal and a complete image signal from a single exposure time period. The overflow image signals and the complete image signals from the pixels may be used to generate a high dynamic range image. While the floating diffusion region in each pixel is not in use, control circuitry may control that pixel to generate a reference signal at the floating diffusion region indicative of pixel-specific dark signal noise. Processing circuitry may mitigate for dark signal non-uniformity across the pixels by correcting the complete image signals using the reference signal to remove dark signal noise in the complete image signals.

Abstract: An imaging system may include an array of image pixels, each image pixel including two photodiodes. A first photodiode may surround a second photodiode. Each image pixel may include two low gain capacitors. A first low gain capacitor may be coupled to a floating diffusion region connected to the two photodiodes via respective transistors. A second low gain capacitor may be coupled to the second photodiode directly or via an interposing transistor. Charge generated by the first photodiode may be separated into an overflow portion stored at the first low gain capacitor and a remaining portion stored at the first photodiode. The overflow charge portion may be used to generated a first signal. The remaining charge portion (along with other charge generated by the first photodiode) may be used to generate a second signal. The charge generated by the second photodiode may be used to generated a third signal.

Abstract: An image sensor may include an imaging pixel, readout circuitry, and amplification circuitry coupled between the imaging pixel and the readout circuitry. Correlated double sampling may be used to sample a reset voltage and a signal voltage from the imaging pixel. The difference between the reset voltage and the signal voltage may reflect the amount of light received by the imaging pixel during an integration time. The amplification circuitry may amplify the difference between the reset voltage and the signal voltage. The amplification circuitry may include a source follower transistor coupled between first and second capacitors, with the second capacitor having a greater capacitance than the first capacitor. The amplification circuitry may be formed only from n-type metal-oxide-semiconductor transistors. The amplification circuitry may consume power dynamically as opposed to consuming static power for minimal power consumption requirements.

Abstract: Imaging circuitry may include circuits for implementing charge mode feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using adjustable weighting circuits to generate corresponding weighted pixel values. The weighted pixels values may then be combined to obtain an output neuron voltage for at least one layer in a neural network. The output neuron voltage may be stored in idle pixels, may be combined with other weighted pixel values, and may be otherwise manipulated prior to being processed in the digital domain. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.