Abstract: Fixed pattern noise (FPN) reduction techniques in image sensors operated with pulse illumination are disclosed herein. In one embodiment, a method includes, during a first sub-exposure period of a frame, (a) operating a first tap of a pixel to capture a first signal corresponding to first charge at a first floating diffusion, the first charge corresponding to first light incident on a photosensor, and (b) operating a second tap of the pixel to capture a first parasitic signal corresponding to FPN at a second floating diffusion. The method further includes, during a second sub-exposure period of the frame, (a) operating the second tap to capture a second signal corresponding to second charge at the second floating diffusion, the second charge corresponding to second light incident on the photosensor, and (b) operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion.

Abstract: Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.

Abstract: Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.

Abstract: An imaging system includes a pixel array with odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit with a sample and hold (SH) circuit and an analog to digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct the image charge photogenerated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure shift during LOFIC readouts during a global transfer period.

Abstract: A gated imaging system includes a pulsed illuminator configured to generate a plurality of light pulses and a pixel circuit. The pixel circuit includes a photodiode configured to collect photogenerated image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a sense node amplifier includes a gate terminal coupled to the floating diffusion, and a storage network coupled between the photodiode and the floating diffusion. The storage network includes a plurality of memory nodes coupled between the photodiode and the floating diffusion in parallel. The storage network is configured to capture a plurality of depth slices between two successive ones of the light pulses.

Abstract: Implementations of a semiconductor device may include a photodiode included in a second epitaxial layer of a semiconductor substrate; light shield coupled over the photodiode; and a first epitaxial layer located in one or more openings in the light shield. The first epitaxial layer and the second epitaxial layer may form a single crystal.

Abstract: An imaging system includes a pixel array with odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit with a sample and hold (SH) circuit and an analog to digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct the image charge photogenerated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure shift during LOFIC readouts during a global transfer period.

Abstract: Implementations of a semiconductor device may include a photodiode included in a second epitaxial layer of a semiconductor substrate; light shield coupled over the photodiode; and a first epitaxial layer located in one or more openings in the light shield. The first epitaxial layer and the second epitaxial layer may form a single crystal.

Abstract: Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to row control circuitry and column readout circuitry. An image pixel in the array may include a charge integration portion having a photodiode, a floating diffusion region, and a capacitor coupled to the floating diffusion region and may include a voltage-domain sampling portion having three capacitors. High light and low light image level and reset level signals may be sampled and stored at the voltage-domain sampling portion before being readout to the column readout circuitry during a readout operation. The high light reset level signal may be sampled and stored during the readout operation.

Abstract: A semiconductor device may include a primary circuit chip and an image sensor chip stacked thereon. The image sensor chip may have a backside illuminated (BSI) surface and a frontside surface opposed to the BSI surface, with the image sensor chip being disposed on the primary circuit chip with the frontside surface facing the primary circuit chip. An auxiliary chip may be disposed on the BSI surface of the image sensor chip and connected to the primary circuit chip through the image sensor chip.

Abstract: Fixed pattern noise (FPN) reduction techniques in image sensors operated with pulse illumination are disclosed herein. In one embodiment, a method includes, during a first sub-exposure period of a frame, (a) operating a first tap of a pixel to capture a first signal corresponding to first charge at a first floating diffusion, the first charge corresponding to first light incident on a photosensor, and (b) operating a second tap of the pixel to capture a first parasitic signal corresponding to FPN at a second floating diffusion. The method further includes, during a second sub-exposure period of the frame, (a) operating the second tap to capture a second signal corresponding to second charge at the second floating diffusion, the second charge corresponding to second light incident on the photosensor, and (b) operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion.

Abstract: Fixed pattern noise (FPN) reduction techniques in image sensors operated with pulse illumination are disclosed herein. In one embodiment, a method includes, during a first sub-exposure period of a frame, (a) operating a first tap of a pixel to capture a first signal corresponding to first charge at a first floating diffusion, the first charge corresponding to first light incident on a photosensor, and (b) operating a second tap of the pixel to capture a first parasitic signal corresponding to FPN at a second floating diffusion. The method further includes, during a second sub-exposure period of the frame, (a) operating the second tap to capture a second signal corresponding to second charge at the second floating diffusion, the second charge corresponding to second light incident on the photosensor, and (b) operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.

Abstract: A time-of-flight (TOF) sensing system may include an illumination module and a sensor module. The sensor module may include an array of sensor pixels, pixel-level readout circuitry, and column-level readout circuitry coupled to the pixel-level readout circuitry via corresponding column lines. Pixel-level readout circuitry may be provided on a per-pixel basis (e.g., dedicated or unshared per-pixel readout circuitry may be provided for each pixel). Pixel-level readout circuitry may include one or more correlated double sampling stages and a storage stage. The storage stage may include a set of capacitors each configured to store different phase data generated by a corresponding pixel for a TOF sensing operation.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel in the array may be a global shutter pixel having a first charge storage node configured to capture scenery information and a second charge storage node configured to capture background information generated as a result of parasitic light and dark noise signals. The first and/or second charge storage nodes may each be provided with an overflow charge storage to provide high dynamic range (HDR) functionality. The background information may be subtracted from the scenery information to cancel out the desired background signal contribution and to obtain an HDR signal with high global shutter efficiency. The charge storage nodes may be implemented as storage diode or storage gate devices. The pixels may be backside illuminated pixels with optical diffracting structures and multiple microlenses formed at the backside to distribute light equally between the two charge storage nodes.

Abstract: A time-of-flight (TOF) sensing system may include an illumination module and a sensor module. The sensor module may include an array of sensor pixels, pixel-level readout circuitry, and column-level readout circuitry coupled to the pixel-level readout circuitry via corresponding column lines. Pixel-level readout circuitry may be provided on a per-pixel basis (e.g., dedicated or unshared per-pixel readout circuitry may be provided for each pixel). Pixel-level readout circuitry may include one or more correlated double sampling stages and a storage stage. The storage stage may include a set of capacitors each configured to store different phase data generated by a corresponding pixel for a TOF sensing operation.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to row control circuitry and column readout circuitry. An image pixel in the array may include a charge integration portion having a photodiode, a floating diffusion region, and a capacitor coupled to the floating diffusion region and may include a voltage-domain sampling portion having three capacitors. High light and low light image level and reset level signals may be sampled and stored at the voltage-domain sampling portion before being readout to the column readout circuitry during a readout operation. The high light reset level signal may be sampled and stored during the readout operation.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.