Abstract: An image sensor may include an array of image pixels that is coupled to column readout circuitry, which may read out charge generated by the image pixels. The column readout circuitry may include a column amplifier having analog memory cells. The analog memory cells may include a high gain capacitor and a low gain capacitor coupled in parallel between a column of the image pixels and an input of the column amplifier. A feedback capacitor may be coupled between the input and an output of the column amplifier. High and low gain select switches respectively coupled to the high and low gain capacitors may allow for the output of high and low gain reset values and image signals, which may be used in correlated double sampling operations and which may increase the dynamic range of the image sensor.

Abstract: Image sensors may include pixel circuitry to enable per-pixel integration time and read-out control. Two transistors may be coupled in series for per-pixel control, with one of the transistors being controlled on a row-by-row basis and the other transistor being controlled on a column-by-column basis. The two transistors in series may be coupled directly to each other without any intervening structures. Two transistors in series between a photodiode and a power supply terminal enables per-pixel control of starting an integration time, two transistors in series between a photodiode and a charge storage region enables per-pixel control of ending an integration time, and two transistors in series between a charge storage region and a floating diffusion region enables per-pixel control of read-out.

Abstract: An image sensor may include an array of image pixels. Control circuitry coupled to the array of pixels may be configured to operate the image pixels in an overflow mode of operation, in which each pixel generates an overflow image signal and a complete image signal from a single exposure time period. The overflow image signals and the complete image signals from the pixels may be used to generate a high dynamic range image. While the floating diffusion region in each pixel is not in use, control circuitry may control that pixel to generate a reference signal at the floating diffusion region indicative of pixel-specific dark signal noise. Processing circuitry may mitigate for dark signal non-uniformity across the pixels by correcting the complete image signals using the reference signal to remove dark signal noise in the complete image signals.

Abstract: An imaging system may include an image sensor having an image sensor. The image sensor may include an image sensor pixel array coupled to row control circuitry and column readout circuitry. The image sensor pixel array may include a plurality of image sensor pixels. Each image sensor pixel may include a photosensitive element configured to generate charge in response to incident light, a first charge storage structure configured to accumulate an overflow portion of the generated charge for a low gain signal and a second charge storage structure configured to store a remaining portion of the generated charge for a high gain signal. Each image sensor pixel may also include a dedicated overflow charge storage structure interposed between the first charge storage structure and a floating diffusion region.

Abstract: An image sensor pixel may include a photodiode that generates first charge for a first frame and second charge for a second frame, first and second storage gates coupled to the photodiode, a floating diffusion coupled to the first storage gate through a first transistor, a second transistor coupled to the second storage gate, and a capacitor coupled to the floating diffusion through a third transistor. The image sensor pixel may output image signals associated with the first charge generated by the photodiode for the first image frame while the photodiode concurrently generates the second charge for the second image frame. The second storage gate may be used to store overflow charge. Overflow charge for the second frame may be stored at the second storage gate while image signals associated with the first image frame are read out from capacitor and the floating diffusion.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel in the array may be a global shutter pixel having a first charge storage node configured to capture scenery information and a second charge storage node configured to capture background information generated as a result of parasitic light and dark noise signals. The first and/or second charge storage nodes may each be provided with an overflow charge storage to provide high dynamic range (HDR) functionality. The background information may be subtracted from the scenery information to cancel out the desired background signal contribution and to obtain an HDR signal with high global shutter efficiency. The charge storage nodes may be implemented as storage diode or storage gate devices. The pixels may be backside illuminated pixels with optical diffracting structures and multiple microlenses formed at the backside to distribute light equally between the two charge storage nodes.

Abstract: An image sensor may include an imaging pixel, readout circuitry, and amplification circuitry coupled between the imaging pixel and the readout circuitry. Correlated double sampling may be used to sample a reset voltage and a signal voltage from the imaging pixel. The difference between the reset voltage and the signal voltage may reflect the amount of light received by the imaging pixel during an integration time. The amplification circuitry may amplify the difference between the reset voltage and the signal voltage. The amplification circuitry may include a source follower transistor coupled between first and second capacitors, with the second capacitor having a greater capacitance than the first capacitor. The amplification circuitry may be formed only from n-type metal-oxide-semiconductor transistors. The amplification circuitry may consume power dynamically as opposed to consuming static power for minimal power consumption requirements.

Abstract: A high dynamic range imaging pixel may include a photodiode that generates charge in response to incident light. Charge from the photodiode may be coupled to a voltage supply and discarded or transferred to a charge storage region such as a storage diode. Alternating between discarding and integrating charge enables flicker mitigation. When the generated charge in the charge storage region exceeds a first charge level, the charge may overflow through a first transistor to a first storage capacitor. When the generated charge exceeds a second charge level that is higher than the first charge level, the charge may overflow through a second transistor. The charge that overflows through the second transistor may alternately be coupled to a voltage supply and drained or transferred to a second storage capacitor for subsequent readout. Diverting more overflow charge to the voltage supply may increase the dynamic range of the pixel.

Abstract: An image sensor may include a plurality of imaging pixels with high dynamic range. Each imaging pixel may have a photodiode, a floating diffusion region, and a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region. Each imaging pixel may also include an overflow capacitor and an overflow transistor interposed between the photodiode and the overflow capacitor. A dual conversion gain transistor may be interposed between the overflow capacitor and the floating diffusion region. To reduce noise associated with operation of the pixel, a ring-shaped conductive layer may form a gate for both the overflow transistor and the dual conversion gain transistor. This common gate may be set to an intermediate level during integration to allow charge to overflow past the overflow transistor to the overflow capacitor. The common gate may also be used to assert the dual conversion gain transistor.

Abstract: An image sensor may include a plurality of imaging pixels with high dynamic range. Each imaging pixel may have a photodiode, a floating diffusion region, and a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region. Each imaging pixel may also include an overflow capacitor and an overflow transistor interposed between the photodiode and the overflow capacitor. A dual conversion gain transistor may be interposed between the overflow capacitor and the floating diffusion region. To reduce noise associated with operation of the pixel, a ring-shaped conductive layer may form a gate for both the overflow transistor and the dual conversion gain transistor. This common gate may be set to an intermediate level during integration to allow charge to overflow past the overflow transistor to the overflow capacitor. The common gate may also be used to assert the dual conversion gain transistor.

Abstract: Various embodiments of the present technology provide a method and apparatus for signal distribution in an image sensor. In various embodiments, the apparatus provides a balanced signal distribution circuit having a plurality of driver circuits, wherein each driver circuit is connected to a logic circuit, distributed either directly below the pixel array or interspersed within the pixel array. A clock distribution network is connected to the logic circuit to provide all the logic circuits with a clock signal substantially simultaneously, which, in turn, controls all of the driver circuits substantially simultaneously and all pixels in the pixel array receive a control signal substantially simultaneously.

Abstract: Image sensors may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates. A first n-epitaxial layer may be formed on a residual substrate; a first p-epitaxial layer may be formed on the first n-epitaxial layer; a second n-epitaxial layer may be formed on the first p-epitaxial layer; a second p-epitaxial layer may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates may be a deep trench that is filled with doped conductive material, lined with gate dielectric liner, and surrounded by a p-doped region. Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.

Abstract: An image sensor pixel may include a photodiode that generates first charge for a first frame and second charge for a second frame, first and second storage gates coupled to the photodiode, a floating diffusion coupled to the first storage gate through a first transistor, a second transistor coupled to the second storage gate, and a capacitor coupled to the floating diffusion through a third transistor. The image sensor pixel may output image signals associated with the first charge generated by the photodiode for the first image frame while the photodiode concurrently generates the second charge for the second image frame. The second storage gate may be used to store overflow charge. Overflow charge for the second frame may be stored at the second storage gate while image signals associated with the first image frame are read out from capacitor and the floating diffusion.

Abstract: Image sensors may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates. A first n-epitaxial layer may be formed on a residual substrate; a first p-epitaxial layer may be formed on the first n-epitaxial layer; a second n-epitaxial layer may be formed on the first p-epitaxial layer; a second p-epitaxial layer may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates may be a deep trench that is filled with doped conductive material, lined with gate dielectric liner, and surrounded by a p-doped region. Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.

Abstract: An image sensor pixel may include a photodiode that generates first charge for a first frame and second charge for a second frame, first and second storage gates coupled to the photodiode, a floating diffusion coupled to the first storage gate through a first transistor, a second transistor coupled to the second storage gate, and a capacitor coupled to the floating diffusion through a third transistor. The image sensor pixel may output image signals associated with the first charge generated by the photodiode for the first image frame while the photodiode concurrently generates the second charge for the second image frame. The second storage gate may be used to store overflow charge. Overflow charge for the second frame may be stored at the second storage gate while image signals associated with the first image frame are read out from capacitor and the floating diffusion.

Abstract: Image sensors may include pixel circuitry to enable per-pixel integration time and read-out control. Two transistors may be coupled in series for per-pixel control, with one of the transistors being controlled on a row-by-row basis and the other transistor being controlled on a column-by-column basis. The two transistors in series may be coupled directly to each other without any intervening structures. Two transistors in series between a photodiode and a power supply terminal enables per-pixel control of starting an integration time, two transistors in series between a photodiode and a charge storage region enables per-pixel control of ending an integration time, and two transistors in series between a charge storage region and a floating diffusion region enables per-pixel control of read-out.

Abstract: An image sensor may include an array of pixels arranged in rows and columns. The array of pixels may operate in a global shutter mode. Each pixel in the array of pixels may have a floating diffusion node for storing charge and may include an active reset circuit that acts as an inverting amplifier and that resets the floating diffusion node to a predetermined reference voltage, which eliminates the need for correlated double sampling readout. A sampling circuit may be coupled to the active reset circuit. The sampling circuit may sample and store signals that correspond to the amount of charge stored at the floating diffusion node. The sampling circuit may pass stored signals to a column sensing line through an amplifier. The amplifier may include a source follower transistor that provides proportional amplification to the stored signals and may include an active reset circuit for resetting the sampling circuit.

Abstract: A pixel may include an inner sub-pixel group and an outer sub-pixel group. The inner sub-pixel group may have a smaller light collecting area than the outer sub-pixel group and therefore be less sensitive to light than the outer sub-pixel group. This may enable the pixel to be used to generate high dynamic range images, even with the sub-pixel groups using the same length integration time. The inner sub-pixel group may be nested within the outer sub-pixel group. Additionally, one or both of the inner sub-pixel group and the outer sub-pixel group can be split into at least two sub-pixels so that the sub-pixel group can be used to gather phase detection data. Adjacent pixels may have sub-pixel groups split in different directions to enable detection of vertical and horizontal edges in a scene.

Abstract: Image sensors may include pixel circuitry to enable per-pixel integration time and read-out control. Two transistors may be coupled in series for per-pixel control, with one of the transistors being controlled on a row-by-row basis and the other transistor being controlled on a column-by-column basis. The two transistors in series may be coupled directly to each other without any intervening structures. Two transistors in series between a photodiode and a power supply terminal enables per-pixel control of starting an integration time, two transistors in series between a photodiode and a charge storage region enables per-pixel control of ending an integration time, and two transistors in series between a charge storage region and a floating diffusion region enables per-pixel control of read-out.

Abstract: An image sensor pixel may include a photodiode, a charge storage region, a floating diffusion node, and a capacitor. A first transistor may be coupled between the photodiode and the charge storage region. A second transistor may be coupled between the charge storage region and the capacitor. The photodiode may generate image signals corresponding to incident light. Multiple image signals may be summed at the charge storage region. The second transistor may determine a portion of the image signal that may be sent to the capacitor for storage. The portion of the image signal that is sent to the capacitor may be a low gain signal. A remaining portion of the image signal may be a high gain signal. The image sensor pixel may also include readout circuitry that is configured to readout low and high gain signals stored at the floating diffusion node in a double-sampling readout operation.